174 	unsigned char dir0, dir0_msn, dir1 = 0;  in early_init_cyrix()  local
177 	dir0_msn = dir0 >> 4; /* identifies CPU "family"   */  in early_init_cyrix()
179 	switch (dir0_msn) {  in early_init_cyrix()
193 	unsigned char dir0, dir0_msn, dir0_lsn, dir1 = 0;  in init_cyrix()  local
213 	Cx86_dir0_msb = dir0_msn = dir0 >> 4; /* identifies CPU "family"   */  in init_cyrix()
226 	switch (dir0_msn) {  in init_cyrix()
320 			dir0_msn++;  /* M II */  in init_cyrix()
339 			dir0_msn = 0;  in init_cyrix()
344 			dir0_msn = 0;  in init_cyrix()
351 		dir0_msn = 7;  in init_cyrix()
354 	strcpy(buf, Cx86_model[dir0_msn & 7]);  in init_cyrix()