Lines Matching +full:0 +full:x180000
18 #define PCI_DEVICE_ID_AMD_17H_ROOT 0x1450
19 #define PCI_DEVICE_ID_AMD_17H_M10H_ROOT 0x15d0
20 #define PCI_DEVICE_ID_AMD_17H_M30H_ROOT 0x1480
21 #define PCI_DEVICE_ID_AMD_17H_M60H_ROOT 0x1630
22 #define PCI_DEVICE_ID_AMD_17H_DF_F4 0x1464
23 #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F4 0x15ec
24 #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F4 0x1494
25 #define PCI_DEVICE_ID_AMD_17H_M60H_DF_F4 0x144c
26 #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F4 0x1444
27 #define PCI_DEVICE_ID_AMD_19H_DF_F4 0x1654
28 #define PCI_DEVICE_ID_AMD_19H_M40H_ROOT 0x14b5
29 #define PCI_DEVICE_ID_AMD_19H_M40H_DF_F4 0x167d
30 #define PCI_DEVICE_ID_AMD_19H_M50H_DF_F4 0x166e
46 #define PCI_DEVICE_ID_AMD_CNB17H_F4 0x1704
103 { 0x00, 0x18, 0x20 },
104 { 0xff, 0x00, 0x20 },
105 { 0xfe, 0x00, 0x20 },
154 err = pci_write_config_dword(root, 0x60, address); in __amd_smn_rw()
156 pr_warn("Error programming SMN address 0x%x.\n", address); in __amd_smn_rw()
160 err = (write ? pci_write_config_dword(root, 0x64, *value) in __amd_smn_rw()
161 : pci_read_config_dword(root, 0x64, value)); in __amd_smn_rw()
163 pr_warn("Error %s SMN address 0x%x.\n", in __amd_smn_rw()
209 ficaa |= reg & 0x3FC; in amd_df_indirect_read()
210 ficaa |= (func & 0x7) << 11; in amd_df_indirect_read()
215 err = pci_write_config_dword(F4, 0x5C, ficaa); in amd_df_indirect_read()
217 pr_warn("Error writing DF Indirect FICAA, FICAA=0x%x\n", ficaa); in amd_df_indirect_read()
221 err = pci_read_config_dword(F4, 0x98, lo); in amd_df_indirect_read()
223 pr_warn("Error reading DF Indirect FICAD LO, FICAA=0x%x.\n", ficaa); in amd_df_indirect_read()
240 u16 roots_per_misc = 0; in amd_cache_northbridges()
241 u16 misc_count = 0; in amd_cache_northbridges()
242 u16 root_count = 0; in amd_cache_northbridges()
246 return 0; in amd_cache_northbridges()
286 for (i = 0; i < amd_northbridges.num; i++) { in amd_cache_northbridges()
313 if (!cpuid_edx(0x80000006)) in amd_cache_northbridges()
314 return 0; in amd_cache_northbridges()
318 * limitations because of E382 and E388 on family 0x10. in amd_cache_northbridges()
320 if (boot_cpu_data.x86 == 0x10 && in amd_cache_northbridges()
321 boot_cpu_data.x86_model >= 0x8 && in amd_cache_northbridges()
322 (boot_cpu_data.x86_model > 0x9 || in amd_cache_northbridges()
323 boot_cpu_data.x86_stepping >= 0x1)) in amd_cache_northbridges()
326 if (boot_cpu_data.x86 == 0x15) in amd_cache_northbridges()
329 /* L3 cache partitioning is supported on family 0x15 */ in amd_cache_northbridges()
330 if (boot_cpu_data.x86 == 0x15) in amd_cache_northbridges()
333 return 0; in amd_cache_northbridges()
345 u32 vendor = device & 0xffff; in early_is_amd_nb()
372 if (boot_cpu_data.x86 < 0x10) in amd_get_mmconfig_range()
399 return 0; in amd_get_subcaches()
401 pci_read_config_dword(link, 0x1d4, &mask); in amd_get_subcaches()
403 return (mask >> (4 * cpu_data(cpu).cpu_core_id)) & 0xf; in amd_get_subcaches()
413 if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING) || mask > 0xf) in amd_set_subcaches()
417 if (reset == 0) { in amd_set_subcaches()
418 pci_read_config_dword(nb->link, 0x1d4, &reset); in amd_set_subcaches()
419 pci_read_config_dword(nb->misc, 0x1b8, &ban); in amd_set_subcaches()
420 ban &= 0x180000; in amd_set_subcaches()
424 if (mask != 0xf) { in amd_set_subcaches()
425 pci_read_config_dword(nb->misc, 0x1b8, ®); in amd_set_subcaches()
426 pci_write_config_dword(nb->misc, 0x1b8, reg & ~0x180000); in amd_set_subcaches()
431 mask |= (0xf ^ (1 << cuid)) << 26; in amd_set_subcaches()
433 pci_write_config_dword(nb->link, 0x1d4, mask); in amd_set_subcaches()
436 pci_read_config_dword(nb->link, 0x1d4, ®); in amd_set_subcaches()
438 pci_read_config_dword(nb->misc, 0x1b8, ®); in amd_set_subcaches()
439 reg &= ~0x180000; in amd_set_subcaches()
440 pci_write_config_dword(nb->misc, 0x1b8, reg | ban); in amd_set_subcaches()
443 return 0; in amd_set_subcaches()
460 for (i = 0; i != amd_northbridges.num; i++) in amd_cache_gart()
461 pci_read_config_dword(node_to_amd_nb(i)->misc, 0x9c, &flush_words[i]); in amd_cache_gart()
480 flushed = 0; in amd_flush_garts()
481 for (i = 0; i < amd_northbridges.num; i++) { in amd_flush_garts()
482 pci_write_config_dword(node_to_amd_nb(i)->misc, 0x9c, in amd_flush_garts()
486 for (i = 0; i < amd_northbridges.num; i++) { in amd_flush_garts()
491 0x9c, &w); in amd_flush_garts()
505 #define MSR_AMD64_IC_CFG 0xC0011021 in __fix_erratum_688()
517 if (boot_cpu_data.x86 != 0x14) in fix_erratum_688()
523 F4 = node_to_amd_nb(0)->link; in fix_erratum_688()
527 if (pci_read_config_dword(F4, 0x164, &val)) in fix_erratum_688()
533 on_each_cpu(__fix_erratum_688, NULL, 0); in fix_erratum_688()
545 return 0; in init_amd_nbs()