518  * Self-test for the INT3 based CALL emulation code.
520  * This exercises int3_emulate_call() to make sure INT3 pt_regs are set up
521  * properly and that there is a stack gap between the INT3 frame and the
523  * stack would corrupt the INT3 IRET frame.
579 	 * Stick the address of the INT3 instruction into int3_selftest_ip,  in int3_selftest()
580 	 * then trigger the INT3, padded with NOPs to match a CALL instruction  in int3_selftest()
583 	asm volatile ("1: int3; nop; nop; nop; nop\n\t"  in int3_selftest()
992 	 * Having observed our INT3 instruction, we now must observe  in poke_int3_handler()
995 	 *	bp_desc = desc			INT3  in poke_int3_handler()
997 	 *	write INT3			if (desc)  in poke_int3_handler()
1006 	 * Discount the INT3. See text_poke_bp_batch().  in poke_int3_handler()
1031 		 * Someone poked an explicit INT3, they'll want to handle it,  in poke_int3_handler()
1069  * Modify multi-byte instruction by using int3 breakpoint on SMP.
1071  * synchronization using int3 breakpoint.
1075  *		- add a int3 trap to the address that will be patched
1081  *		- replace the first byte (int3) by the first byte of
1092 	unsigned char int3 = INT3_INSN_OPCODE;  in text_poke_bp_batch()  local
1101 	 * Corresponding read barrier in int3 notifier for making sure the  in text_poke_bp_batch()
1107 	 * First step: add a int3 trap to the address that will be patched.  in text_poke_bp_batch()
1111 		text_poke(text_poke_addr(&tp[i]), &int3, INT3_INSN_SIZE);  in text_poke_bp_batch()
1137 		 *   - write INT3 byte  in text_poke_bp_batch()
1141 		 * INT3 and handler and not hit the old or new instruction.  in text_poke_bp_batch()
1142 		 * Intel PT outputs FUP/TIP packets for the INT3, so the flow  in text_poke_bp_batch()
1149 		 * either the old instruction flow or FUP/TIP of INT3. After the  in text_poke_bp_batch()
1151 		 * new instruction flow or FUP/TIP of INT3. Thus decoders can  in text_poke_bp_batch()
1171 	 * Third step: replace the first byte (int3) by the first byte of  in text_poke_bp_batch()