Lines Matching +full:0 +full:x1b00
15 #define MSR_ARCH_PERFMON_PERFCTR0 0xc1
16 #define MSR_ARCH_PERFMON_PERFCTR1 0xc2
18 #define MSR_ARCH_PERFMON_EVENTSEL0 0x186
19 #define MSR_ARCH_PERFMON_EVENTSEL1 0x187
21 #define ARCH_PERFMON_EVENTSEL_EVENT 0x000000FFULL
22 #define ARCH_PERFMON_EVENTSEL_UMASK 0x0000FF00ULL
31 #define ARCH_PERFMON_EVENTSEL_CMASK 0xFF000000ULL
44 (0xFULL << AMD64_EVENTSEL_INT_CORE_SEL_SHIFT)
47 (ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
53 (0xFULL << AMD64_L3_SLICE_SHIFT)
55 (0x7ULL << AMD64_L3_SLICE_SHIFT)
59 (0xFFULL << AMD64_L3_THREAD_SHIFT)
61 (0x3ULL << AMD64_L3_THREAD_SHIFT)
68 (0x7ULL << AMD64_L3_COREID_SHIFT)
94 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c
95 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8)
96 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 0
103 #define PEBS_DATACFG_MEMINFO BIT_ULL(0)
208 #define MSR_ARCH_PERFMON_FIXED_CTR_CTRL 0x38d
219 * The pseudo event-code for a fixed-mode PMC must be 0x00.
220 * The pseudo umask-code is 0xX. The X equals the index of the fixed
221 * counter + 1, e.g., the fixed counter 2 has the pseudo-encoding 0x0300.
227 #define MSR_ARCH_PERFMON_FIXED_CTR0 0x309
228 #define INTEL_PMC_IDX_FIXED_INSTRUCTIONS (INTEL_PMC_IDX_FIXED + 0)
231 #define MSR_ARCH_PERFMON_FIXED_CTR1 0x30a
234 /* CPU_CLK_Unhalted.Ref: event=0x00,umask=0x3 (pseudo-encoding) */
235 #define MSR_ARCH_PERFMON_FIXED_CTR2 0x30b
239 /* TOPDOWN.SLOTS: event=0x00,umask=0x4 (pseudo-encoding) */
240 #define MSR_ARCH_PERFMON_FIXED_CTR3 0x30c
260 #define INTEL_PMC_IDX_TD_RETIRING (INTEL_PMC_IDX_METRIC_BASE + 0)
269 #define INTEL_PMC_MSK_TOPDOWN ((0xffull << INTEL_PMC_IDX_METRIC_BASE) | \
277 * For the metric events, the pseudo event-code is 0x00.
279 * space, 0x80.
281 #define INTEL_TD_SLOTS 0x0400 /* TOPDOWN.SLOTS */
283 #define INTEL_TD_METRIC_RETIRING 0x8000 /* Retiring metric */
284 #define INTEL_TD_METRIC_BAD_SPEC 0x8100 /* Bad speculation metric */
285 #define INTEL_TD_METRIC_FE_BOUND 0x8200 /* FE bound metric */
286 #define INTEL_TD_METRIC_BE_BOUND 0x8300 /* BE bound metric */
288 #define INTEL_TD_METRIC_HEAVY_OPS 0x8400 /* Heavy Operations metric */
289 #define INTEL_TD_METRIC_BR_MISPREDICT 0x8500 /* Branch Mispredict metric */
290 #define INTEL_TD_METRIC_FETCH_LAT 0x8600 /* Fetch Latency metric */
291 #define INTEL_TD_METRIC_MEM_BOUND 0x8700 /* Memory bound metric */
307 (~(0x1ull << bit) & INTEL_PMC_MSK_TOPDOWN)
336 * Pseudo-encoding the guest LBR event as event=0x00,umask=0x1b,
339 #define INTEL_FIXED_VLBR_EVENT 0x1b00
372 #define IBS_CPUID_FEATURES 0x8000001b
376 * bit 0 is used to indicate the existence of IBS.
378 #define IBS_CAPS_AVAIL (1U<<0)
397 #define IBSCTL 0x1cc
399 #define IBSCTL_LVT_OFFSET_MASK 0x0F
405 #define IBS_FETCH_CNT 0xFFFF0000ULL
406 #define IBS_FETCH_MAX_CNT 0x0000FFFFULL
413 #define IBS_OP_CUR_CNT (0xFFF80ULL<<32)
414 #define IBS_OP_CUR_CNT_RAND (0x0007FULL<<32)
418 #define IBS_OP_MAX_CNT 0x0000FFFFULL
419 #define IBS_OP_MAX_CNT_EXT 0x007FFFFFULL /* not a register bit mask */
420 #define IBS_OP_MAX_CNT_EXT_MASK (0x7FULL<<20) /* separate upper 7 bits */
426 static inline u32 get_ibs_caps(void) { return 0; } in get_ibs_caps()
434 * unused and ABI specified to be 0, so nobody should care what we do with
462 (regs)->sp = (unsigned long)__builtin_frame_address(0); \
464 regs->flags = 0; \
486 memset(cap, 0, sizeof(*cap)); in perf_get_x86_pmu_capability()