Lines Matching defs:cpu_hw_events

226 struct cpu_hw_events {  struct
230 	struct perf_event	*events[X86_PMC_IDX_MAX]; /* in counter order */
231 	unsigned long		active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
232 	unsigned long		dirty[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
233 	int			enabled;
235 	int			n_events; /* the # of events in the below arrays */
236 	int			n_added;  /* the # last events in the below arrays;
238 	int			n_txn;    /* the # last events in the below arrays;
240 	int			n_txn_pair;
241 	int			n_txn_metric;
242 	int			assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
243 	u64			tags[X86_PMC_IDX_MAX];
245 	struct perf_event	*event_list[X86_PMC_IDX_MAX]; /* in enabled order */
246 	struct event_constraint	*event_constraint[X86_PMC_IDX_MAX];
248 	int			n_excl; /* the number of exclusive events */
250 	unsigned int		txn_flags;
251 	int			is_fake;
256 	struct debug_store	*ds;
257 	void			*ds_pebs_vaddr;
258 	void			*ds_bts_vaddr;
259 	u64			pebs_enabled;
260 	int			n_pebs;
261 	int			n_large_pebs;
262 	int			n_pebs_via_pt;
263 	int			pebs_output;
266 	u64			pebs_data_cfg;
267 	u64			active_pebs_data_cfg;
268 	int			pebs_record_size;
273 	int				lbr_users;
274 	int				lbr_pebs_users;
275 	struct perf_branch_stack	lbr_stack;
276 	struct perf_branch_entry	lbr_entries[MAX_LBR_ENTRIES];
277 	union {
281 	u64				br_sel;
282 	void				*last_task_ctx;
283 	int				last_log_id;
284 	int				lbr_select;
285 	void				*lbr_xsave;
290 	u64				intel_ctrl_guest_mask;
291 	u64				intel_ctrl_host_mask;
292 	struct perf_guest_switch_msr	guest_switch_msrs[X86_PMC_IDX_MAX];
297 	u64				intel_cp_status;
303 	struct intel_shared_regs	*shared_regs;
307 	struct event_constraint *constraint_list; /* in enable order */
308 	struct intel_excl_cntrs		*excl_cntrs;
309 	int excl_thread_id; /* 0 or 1 */
314 	u64				tfa_shadow;
320 	int				n_metric;
325 	struct amd_nb			*amd_nb;
327 	u64				perf_ctr_virt_mask;
328 	int				n_pair; /* Large increment events */
330 	void				*kfree_on_online[X86_PERF_KFREE_MAX];
332 	struct pmu			*pmu;