Lines Matching +full:sha +full:- +full:1
2 * Intel SHA Extensions optimized implementation of a SHA-1 update function
58 #define DIGEST_PTR %rdi /* 1st arg */
76 * Intel SHA Extensions optimized implementation of a SHA-1 update function
86 * The non-indented lines are instructions related to the message schedule.
107 pinsrd $3, 1*16(DIGEST_PTR), E0
117 movdqa ABCD, (1*16)(%rsp)
119 /* Rounds 0-3 */
126 /* Rounds 4-7 */
127 movdqu 1*16(DATA_PTR), MSG1
134 /* Rounds 8-11 */
143 /* Rounds 12-15 */
153 /* Rounds 16-19 */
161 /* Rounds 20-23 */
165 sha1rnds4 $1, E1, ABCD
169 /* Rounds 24-27 */
173 sha1rnds4 $1, E0, ABCD
177 /* Rounds 28-31 */
181 sha1rnds4 $1, E1, ABCD
185 /* Rounds 32-35 */
189 sha1rnds4 $1, E0, ABCD
193 /* Rounds 36-39 */
197 sha1rnds4 $1, E1, ABCD
201 /* Rounds 40-43 */
209 /* Rounds 44-47 */
217 /* Rounds 48-51 */
225 /* Rounds 52-55 */
233 /* Rounds 56-59 */
241 /* Rounds 60-63 */
249 /* Rounds 64-67 */
257 /* Rounds 68-71 */
264 /* Rounds 72-75 */
270 /* Rounds 76-79 */
277 paddd (1*16)(%rsp), ABCD
287 pextrd $3, E0, 1*16(DIGEST_PTR)