Lines Matching +full:0 +full:x1c000
47 #define __SAVE __asm__ __volatile__("save %sp, -0x40, %sp\n\t")
53 int count = 0; in die_if_kernel()
81 !(((unsigned long) rw) & 0x7)) { in die_if_kernel()
96 if(type < 0x80) { in do_hw_interrupt()
106 (void __user *)regs->pc, type - 0x80); in do_hw_interrupt()
141 #if 0 in do_memaccess_unaligned()
147 /* FIXME: Should dig out mna address */ (void *)0, in do_memaccess_unaligned()
151 static unsigned long init_fsr = 0x0UL;
153 { ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL,
154 ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL,
155 ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL,
156 ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL };
173 fpsave(&fptask->thread.float_regs[0], &fptask->thread.fsr, in do_fpd_trap()
174 &fptask->thread.fpqueue[0], &fptask->thread.fpqdepth); in do_fpd_trap()
178 fpload(¤t->thread.float_regs[0], ¤t->thread.fsr); in do_fpd_trap()
181 fpload(&init_fregs[0], &init_fsr); in do_fpd_trap()
186 fpload(&init_fregs[0], &init_fsr); in do_fpd_trap()
189 fpload(¤t->thread.float_regs[0], ¤t->thread.fsr); in do_fpd_trap()
205 int ret = 0;
222 fpsave(&fake_regs[0], &fake_fsr, &fake_queue[0], &fake_depth);
226 fpsave(&fpt->thread.float_regs[0], &fpt->thread.fsr,
227 &fpt->thread.fpqueue[0], &fpt->thread.fpqdepth);
232 switch ((fpt->thread.fsr & 0x1c000)) {
257 fpload(¤t->thread.float_regs[0], ¤t->thread.fsr);
282 if ((fsr & 0x1c000) == (1 << 14)) {
283 if (fsr & 0x10)
285 else if (fsr & 0x08)
287 else if (fsr & 0x04)
289 else if (fsr & 0x02)
291 else if (fsr & 0x01)
299 if(calls > 0)
300 calls=0;