Lines Matching +full:multi +full:- +full:bit

1 # SPDX-License-Identifier: GPL-2.0
9 	  Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
12 	  On other systems (such as the SH-3 and 4) where an MMU exists,
72 config 29BIT
73 	def_bool !32BIT
76 config 32BIT
81 	bool "Support 32-bit physical addressing through PMB"
83 	select 32BIT
87 	  32-bits through the SH-4A PMB. If this is not set, legacy
88 	  29-bit physical addressing will be used.
108 	bool "Non-Uniform Memory Access (NUMA) Support"
167 	  This enables 8kB pages as supported by SH-X2 and later MMUs.
173 	  This enables 16kB pages on MMU-less SH systems.
179 	  This enables support for 64kB pages, possible on all SH-4
212 	bool "Multi-core scheduler support"
216 	  Multi-core scheduler support improves the CPU scheduler's decision
217 	  making when dealing with multi-core CPU chips at a cost of slightly
235 	bool "Write-back"
238 	bool "Write-through"
240 	  Selecting this option will configure the caches in write-through
241 	  mode, as opposed to the default write-back configuration.
243 	  Since there's sill some aliasing issues on SH-4, this option will