Lines Matching +full:default +full:- +full:on

1 # SPDX-License-Identifier: GPL-2.0
6 	depends on !CPU_SH2
7 	default y
9 	  Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
10 	  boot on these systems, this option must not be set.
12 	  On other systems (such as the SH-3 and 4) where an MMU exists,
13 	  turning this off will boot the kernel on these machines with the
18 	default "0x80000000" if MMU
19 	default "0x00000000"
24 	default "9" if PAGE_SIZE_16KB
26 	default "7" if PAGE_SIZE_64KB
28 	default "14" if !MMU
29 	default "11"
46 	default "0x08000000"
58 	  value on any of the known systems will only lead to disaster.
62 	default "0x04000000"
64 	  This sets the default memory size assumed by your SH kernel. It can
65 	  be overridden as normal by the 'mem=' argument on the kernel command
67 	  as 0x04000000 which was the default value before this became
78 	default !MMU
81 	bool "Support 32-bit physical addressing through PMB"
82 	depends on MMU && CPU_SH4A && !CPU_SH4AL_DSP
87 	  32-bits through the SH-4A PMB. If this is not set, legacy
88 	  29-bit physical addressing will be used.
92 	depends on (CPU_SHX2 || CPU_SHX3) && MMU
96 	depends on MMU && (CPU_SH3 || CPU_SH4)
97 	default y
105 	  (the default value) say Y.
108 	bool "Non-Uniform Memory Access (NUMA) Support"
109 	depends on MMU && SYS_SUPPORTS_NUMA
111 	default n
121 	default "3" if CPU_SUBTYPE_SHX3
122 	default "1"
123 	depends on NUMA
127 	depends on !NUMA
141 	depends on MEMORY_HOTPLUG
145        depends on X2TLB
156 	default PAGE_SIZE_4KB
161 	  This is the default page size used by all SuperH CPUs.
165 	depends on !MMU || X2TLB
167 	  This enables 8kB pages as supported by SH-X2 and later MMUs.
171 	depends on !MMU
173 	  This enables 16kB pages on MMU-less SH systems.
177 	depends on !MMU || CPU_SH4
179 	  This enables support for 64kB pages, possible on all SH-4
186 	depends on HUGETLB_PAGE
187 	default HUGETLB_PAGE_SIZE_1MB if PAGE_SIZE_64KB
188 	default HUGETLB_PAGE_SIZE_64K
192 	depends on !PAGE_SIZE_64KB
196 	depends on X2TLB
203 	depends on X2TLB
207 	depends on X2TLB
212 	bool "Multi-core scheduler support"
213 	depends on SMP
214 	default y
216 	  Multi-core scheduler support improves the CPU scheduler's decision
217 	  making when dealing with multi-core CPU chips at a cost of slightly
226 	depends on CPU_SUBTYPE_SH7705
227 	default y
231 	default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4
232 	default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A)
235 	bool "Write-back"
238 	bool "Write-through"
240 	  Selecting this option will configure the caches in write-through
241 	  mode, as opposed to the default write-back configuration.
243 	  Since there's sill some aliasing issues on SH-4, this option will