Lines Matching +full:fu540 +full:- +full:c000 +full:- +full:prci
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu740-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu740-c000", "sifive,fu740";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
29 i-cache-sets = <128>;
30 i-cache-size = <16384>;
31 next-level-cache = <&ccache>;
35 cpu0_intc: interrupt-controller {
36 #interrupt-cells = <1>;
37 compatible = "riscv,cpu-intc";
38 interrupt-controller;
43 d-cache-block-size = <64>;
44 d-cache-sets = <64>;
45 d-cache-size = <32768>;
46 d-tlb-sets = <1>;
47 d-tlb-size = <40>;
49 i-cache-block-size = <64>;
50 i-cache-sets = <128>;
51 i-cache-size = <32768>;
52 i-tlb-sets = <1>;
53 i-tlb-size = <40>;
54 mmu-type = "riscv,sv39";
55 next-level-cache = <&ccache>;
58 tlb-split;
59 cpu1_intc: interrupt-controller {
60 #interrupt-cells = <1>;
61 compatible = "riscv,cpu-intc";
62 interrupt-controller;
67 d-cache-block-size = <64>;
68 d-cache-sets = <64>;
69 d-cache-size = <32768>;
70 d-tlb-sets = <1>;
71 d-tlb-size = <40>;
73 i-cache-block-size = <64>;
74 i-cache-sets = <128>;
75 i-cache-size = <32768>;
76 i-tlb-sets = <1>;
77 i-tlb-size = <40>;
78 mmu-type = "riscv,sv39";
79 next-level-cache = <&ccache>;
82 tlb-split;
83 cpu2_intc: interrupt-controller {
84 #interrupt-cells = <1>;
85 compatible = "riscv,cpu-intc";
86 interrupt-controller;
91 d-cache-block-size = <64>;
92 d-cache-sets = <64>;
93 d-cache-size = <32768>;
94 d-tlb-sets = <1>;
95 d-tlb-size = <40>;
97 i-cache-block-size = <64>;
98 i-cache-sets = <128>;
99 i-cache-size = <32768>;
100 i-tlb-sets = <1>;
101 i-tlb-size = <40>;
102 mmu-type = "riscv,sv39";
103 next-level-cache = <&ccache>;
106 tlb-split;
107 cpu3_intc: interrupt-controller {
108 #interrupt-cells = <1>;
109 compatible = "riscv,cpu-intc";
110 interrupt-controller;
115 d-cache-block-size = <64>;
116 d-cache-sets = <64>;
117 d-cache-size = <32768>;
118 d-tlb-sets = <1>;
119 d-tlb-size = <40>;
121 i-cache-block-size = <64>;
122 i-cache-sets = <128>;
123 i-cache-size = <32768>;
124 i-tlb-sets = <1>;
125 i-tlb-size = <40>;
126 mmu-type = "riscv,sv39";
127 next-level-cache = <&ccache>;
130 tlb-split;
131 cpu4_intc: interrupt-controller {
132 #interrupt-cells = <1>;
133 compatible = "riscv,cpu-intc";
134 interrupt-controller;
139 #address-cells = <2>;
140 #size-cells = <2>;
141 compatible = "simple-bus";
143 plic0: interrupt-controller@c000000 {
144 #interrupt-cells = <1>;
145 #address-cells = <0>;
146 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
149 interrupt-controller;
150 interrupts-extended = <
157 prci: clock-controller@10000000 { label
158 compatible = "sifive,fu740-c000-prci";
161 #clock-cells = <1>;
162 #reset-cells = <1>;
165 compatible = "sifive,fu740-c000-uart", "sifive,uart0";
167 interrupt-parent = <&plic0>;
169 clocks = <&prci PRCI_CLK_PCLK>;
173 compatible = "sifive,fu740-c000-uart", "sifive,uart0";
175 interrupt-parent = <&plic0>;
177 clocks = <&prci PRCI_CLK_PCLK>;
181 compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
183 interrupt-parent = <&plic0>;
185 clocks = <&prci PRCI_CLK_PCLK>;
186 reg-shift = <2>;
187 reg-io-width = <1>;
188 #address-cells = <1>;
189 #size-cells = <0>;
193 compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
195 interrupt-parent = <&plic0>;
197 clocks = <&prci PRCI_CLK_PCLK>;
198 reg-shift = <2>;
199 reg-io-width = <1>;
200 #address-cells = <1>;
201 #size-cells = <0>;
205 compatible = "sifive,fu740-c000-spi", "sifive,spi0";
208 interrupt-parent = <&plic0>;
210 clocks = <&prci PRCI_CLK_PCLK>;
211 #address-cells = <1>;
212 #size-cells = <0>;
216 compatible = "sifive,fu740-c000-spi", "sifive,spi0";
219 interrupt-parent = <&plic0>;
221 clocks = <&prci PRCI_CLK_PCLK>;
222 #address-cells = <1>;
223 #size-cells = <0>;
227 compatible = "sifive,fu740-c000-spi", "sifive,spi0";
229 interrupt-parent = <&plic0>;
231 clocks = <&prci PRCI_CLK_PCLK>;
232 #address-cells = <1>;
233 #size-cells = <0>;
237 compatible = "sifive,fu540-c000-gem";
238 interrupt-parent = <&plic0>;
242 local-mac-address = [00 00 00 00 00 00];
243 clock-names = "pclk", "hclk";
244 clocks = <&prci PRCI_CLK_GEMGXLPLL>,
245 <&prci PRCI_CLK_GEMGXLPLL>;
246 #address-cells = <1>;
247 #size-cells = <0>;
251 compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
253 interrupt-parent = <&plic0>;
255 clocks = <&prci PRCI_CLK_PCLK>;
256 #pwm-cells = <3>;
260 compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
262 interrupt-parent = <&plic0>;
264 clocks = <&prci PRCI_CLK_PCLK>;
265 #pwm-cells = <3>;
268 ccache: cache-controller@2010000 {
269 compatible = "sifive,fu740-c000-ccache", "cache";
270 cache-block-size = <64>;
271 cache-level = <2>;
272 cache-sets = <2048>;
273 cache-size = <2097152>;
274 cache-unified;
275 interrupt-parent = <&plic0>;
280 compatible = "sifive,fu740-c000-gpio", "sifive,gpio0";
281 interrupt-parent = <&plic0>;
286 gpio-controller;
287 #gpio-cells = <2>;
288 interrupt-controller;
289 #interrupt-cells = <2>;
290 clocks = <&prci PRCI_CLK_PCLK>;
294 compatible = "sifive,fu740-pcie";
295 #address-cells = <3>;
296 #size-cells = <2>;
297 #interrupt-cells = <1>;
301 reg-names = "dbi", "config", "mgmt";
303 dma-coherent;
304 bus-range = <0x0 0xff>;
309 num-lanes = <0x8>;
311 interrupt-names = "msi", "inta", "intb", "intc", "intd";
312 interrupt-parent = <&plic0>;
313 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
314 interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,
318 clock-names = "pcie_aux";
319 clocks = <&prci PRCI_CLK_PCIE_AUX>;
320 pwren-gpios = <&gpio 5 0>;
321 reset-gpios = <&gpio 8 0>;
322 resets = <&prci 4>;