Lines Matching +full:fu540 +full:- +full:c000
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
7 #address-cells = <2>;
8 #size-cells = <2>;
10 compatible = "microchip,mpfs-icicle-kit";
16 #address-cells = <1>;
17 #size-cells = <0>;
20 clock-frequency = <0>;
23 i-cache-block-size = <64>;
24 i-cache-sets = <128>;
25 i-cache-size = <16384>;
30 cpu0_intc: interrupt-controller {
31 #interrupt-cells = <1>;
32 compatible = "riscv,cpu-intc";
33 interrupt-controller;
38 clock-frequency = <0>;
39 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
40 d-cache-block-size = <64>;
41 d-cache-sets = <64>;
42 d-cache-size = <32768>;
43 d-tlb-sets = <1>;
44 d-tlb-size = <32>;
46 i-cache-block-size = <64>;
47 i-cache-sets = <64>;
48 i-cache-size = <32768>;
49 i-tlb-sets = <1>;
50 i-tlb-size = <32>;
51 mmu-type = "riscv,sv39";
54 tlb-split;
57 cpu1_intc: interrupt-controller {
58 #interrupt-cells = <1>;
59 compatible = "riscv,cpu-intc";
60 interrupt-controller;
65 clock-frequency = <0>;
66 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
67 d-cache-block-size = <64>;
68 d-cache-sets = <64>;
69 d-cache-size = <32768>;
70 d-tlb-sets = <1>;
71 d-tlb-size = <32>;
73 i-cache-block-size = <64>;
74 i-cache-sets = <64>;
75 i-cache-size = <32768>;
76 i-tlb-sets = <1>;
77 i-tlb-size = <32>;
78 mmu-type = "riscv,sv39";
81 tlb-split;
84 cpu2_intc: interrupt-controller {
85 #interrupt-cells = <1>;
86 compatible = "riscv,cpu-intc";
87 interrupt-controller;
92 clock-frequency = <0>;
93 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
94 d-cache-block-size = <64>;
95 d-cache-sets = <64>;
96 d-cache-size = <32768>;
97 d-tlb-sets = <1>;
98 d-tlb-size = <32>;
100 i-cache-block-size = <64>;
101 i-cache-sets = <64>;
102 i-cache-size = <32768>;
103 i-tlb-sets = <1>;
104 i-tlb-size = <32>;
105 mmu-type = "riscv,sv39";
108 tlb-split;
111 cpu3_intc: interrupt-controller {
112 #interrupt-cells = <1>;
113 compatible = "riscv,cpu-intc";
114 interrupt-controller;
119 clock-frequency = <0>;
120 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
121 d-cache-block-size = <64>;
122 d-cache-sets = <64>;
123 d-cache-size = <32768>;
124 d-tlb-sets = <1>;
125 d-tlb-size = <32>;
127 i-cache-block-size = <64>;
128 i-cache-sets = <64>;
129 i-cache-size = <32768>;
130 i-tlb-sets = <1>;
131 i-tlb-size = <32>;
132 mmu-type = "riscv,sv39";
135 tlb-split;
137 cpu4_intc: interrupt-controller {
138 #interrupt-cells = <1>;
139 compatible = "riscv,cpu-intc";
140 interrupt-controller;
146 #address-cells = <2>;
147 #size-cells = <2>;
148 compatible = "simple-bus";
151 cache-controller@2010000 {
152 compatible = "sifive,fu540-c000-ccache", "cache";
153 cache-block-size = <64>;
154 cache-level = <2>;
155 cache-sets = <1024>;
156 cache-size = <2097152>;
157 cache-unified;
158 interrupt-parent = <&plic>;
166 interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
173 plic: interrupt-controller@c000000 {
174 #interrupt-cells = <1>;
175 compatible = "sifive,plic-1.0.0";
178 interrupt-controller;
179 interrupts-extended = <&cpu0_intc 11
187 compatible = "sifive,fu540-c000-pdma";
189 interrupt-parent = <&plic>;
191 #dma-cells = <1>;
195 compatible = "fixed-clock";
196 #clock-cells = <0>;
197 clock-frequency = <600000000>;
198 clock-output-names = "msspllclk";
202 compatible = "microchip,mpfs-clkcfg";
204 reg-names = "mss_sysreg";
206 #clock-cells = <1>;
207 clock-output-names = "cpu", "axi", "ahb", "envm", /* 0-3 */
208 "mac0", "mac1", "mmc", "timer", /* 4-7 */
209 "mmuart0", "mmuart1", "mmuart2", "mmuart3", /* 8-11 */
210 "mmuart4", "spi0", "spi1", "i2c0", /* 12-15 */
211 "i2c1", "can0", "can1", "usb", /* 16-19 */
212 "rsvd", "rtc", "qspi", "gpio0", /* 20-23 */
213 "gpio1", "gpio2", "ddrc", "fic0", /* 24-27 */
214 "fic1", "fic2", "fic3", "athena", "cfm"; /* 28-32 */
220 reg-io-width = <4>;
221 reg-shift = <2>;
222 interrupt-parent = <&plic>;
224 current-speed = <115200>;
232 reg-io-width = <4>;
233 reg-shift = <2>;
234 interrupt-parent = <&plic>;
236 current-speed = <115200>;
244 reg-io-width = <4>;
245 reg-shift = <2>;
246 interrupt-parent = <&plic>;
248 current-speed = <115200>;
256 reg-io-width = <4>;
257 reg-shift = <2>;
258 interrupt-parent = <&plic>;
260 current-speed = <115200>;
268 interrupt-parent = <&plic>;
270 pinctrl-names = "default";
272 bus-width = <4>;
273 cap-mmc-highspeed;
274 mmc-ddr-3_3v;
275 max-frequency = <200000000>;
276 non-removable;
277 no-sd;
278 no-sdio;
279 voltage-ranges = <3300 3300>;
286 interrupt-parent = <&plic>;
288 pinctrl-names = "default";
290 bus-width = <4>;
291 disable-wp;
292 cap-sd-highspeed;
293 card-detect-delay = <200>;
294 sd-uhs-sdr12;
295 sd-uhs-sdr25;
296 sd-uhs-sdr50;
297 sd-uhs-sdr104;
298 max-frequency = <200000000>;
305 interrupt-parent = <&plic>;
307 local-mac-address = [00 00 00 00 00 00];
309 clock-names = "pclk", "hclk";
311 #address-cells = <1>;
312 #size-cells = <0>;
318 interrupt-parent = <&plic>;
320 local-mac-address = [00 00 00 00 00 00];
323 clock-names = "pclk", "hclk";
324 #address-cells = <1>;
325 #size-cells = <0>;