Lines Matching +full:reg +full:- +full:io +full:- +full:width
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
6 #include <dt-bindings/clock/k210-clk.h>
7 #include <dt-bindings/pinctrl/k210-fpioa.h>
8 #include <dt-bindings/reset/k210-rst.h>
12 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
15 #address-cells = <1>;
16 #size-cells = <1>;
17 compatible = "canaan,kendryte-k210";
28 * Since this is a non-ratified draft specification, the kernel does not
33 #address-cells = <1>;
34 #size-cells = <0>;
35 timebase-frequency = <7800000>;
39 reg = <0>;
41 mmu-type = "riscv,none";
42 i-cache-block-size = <64>;
43 i-cache-size = <0x8000>;
44 d-cache-block-size = <64>;
45 d-cache-size = <0x8000>;
46 cpu0_intc: interrupt-controller {
47 #interrupt-cells = <1>;
48 interrupt-controller;
49 compatible = "riscv,cpu-intc";
55 reg = <1>;
57 mmu-type = "riscv,none";
58 i-cache-block-size = <64>;
59 i-cache-size = <0x8000>;
60 d-cache-block-size = <64>;
61 d-cache-size = <0x8000>;
62 cpu1_intc: interrupt-controller {
63 #interrupt-cells = <1>;
64 interrupt-controller;
65 compatible = "riscv,cpu-intc";
72 compatible = "canaan,k210-sram";
73 reg = <0x80000000 0x400000>,
76 reg-names = "sram0", "sram1", "aisram";
80 clock-names = "sram0", "sram1", "aisram";
85 compatible = "fixed-clock";
86 #clock-cells = <0>;
87 clock-frequency = <26000000>;
92 #address-cells = <1>;
93 #size-cells = <1>;
94 compatible = "simple-bus";
96 interrupt-parent = <&plic0>;
99 reg = <0x1000 0x1000>;
100 read-only;
104 compatible = "canaan,k210-clint", "sifive,clint0";
105 reg = <0x2000000 0xC000>;
106 interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
110 plic0: interrupt-controller@c000000 {
111 #interrupt-cells = <1>;
112 #address-cells = <0>;
113 compatible = "canaan,k210-plic", "sifive,plic-1.0.0";
114 reg = <0xC000000 0x4000000>;
115 interrupt-controller;
116 interrupts-extended = <&cpu0_intc 11 &cpu1_intc 11>;
121 compatible = "canaan,k210-uarths", "sifive,uart0";
122 reg = <0x38000000 0x1000>;
127 gpio0: gpio-controller@38001000 {
128 #interrupt-cells = <2>;
129 #gpio-cells = <2>;
130 compatible = "canaan,k210-gpiohs", "sifive,gpio0";
131 reg = <0x38001000 0x1000>;
132 interrupt-controller;
137 gpio-controller;
141 dmac0: dma-controller@50000000 {
142 compatible = "snps,axi-dma-1.01a";
143 reg = <0x50000000 0x1000>;
145 #dma-cells = <1>;
147 clock-names = "core-clk", "cfgr-clk";
149 dma-channels = <6>;
150 snps,dma-masters = <2>;
152 snps,data-width = <5>;
153 snps,block-size = <0x200000 0x200000 0x200000
155 snps,axi-max-burst-len = <256>;
159 #address-cells = <1>;
160 #size-cells = <1>;
161 compatible = "simple-pm-bus";
166 #address-cells = <1>;
167 #size-cells = <0>;
168 compatible = "snps,dw-apb-gpio";
169 reg = <0x50200000 0x80>;
172 clock-names = "bus", "db";
175 gpio1_0: gpio-port@0 {
176 #gpio-cells = <2>;
177 #interrupt-cells = <2>;
178 compatible = "snps,dw-apb-gpio-port";
179 reg = <0>;
180 interrupt-controller;
182 gpio-controller;
188 compatible = "snps,dw-apb-uart";
189 reg = <0x50210000 0x100>;
193 clock-names = "baudclk", "apb_pclk";
195 reg-io-width = <4>;
196 reg-shift = <2>;
197 dcd-override;
198 dsr-override;
199 cts-override;
200 ri-override;
204 compatible = "snps,dw-apb-uart";
205 reg = <0x50220000 0x100>;
209 clock-names = "baudclk", "apb_pclk";
211 reg-io-width = <4>;
212 reg-shift = <2>;
213 dcd-override;
214 dsr-override;
215 cts-override;
216 ri-override;
220 compatible = "snps,dw-apb-uart";
221 reg = <0x50230000 0x100>;
225 clock-names = "baudclk", "apb_pclk";
227 reg-io-width = <4>;
228 reg-shift = <2>;
229 dcd-override;
230 dsr-override;
231 cts-override;
232 ri-override;
236 compatible = "canaan,k210-spi";
237 spi-slave;
238 reg = <0x50240000 0x100>;
239 #address-cells = <0>;
240 #size-cells = <0>;
244 clock-names = "ssi_clk", "pclk";
246 spi-max-frequency = <25000000>;
250 compatible = "snps,designware-i2s";
251 reg = <0x50250000 0x200>;
254 clock-names = "i2sclk";
259 compatible = "snps,designware-i2s";
260 reg = <0x50260000 0x200>;
263 clock-names = "i2sclk";
268 compatible = "snps,designware-i2s";
269 reg = <0x50270000 0x200>;
272 clock-names = "i2sclk";
277 compatible = "snps,designware-i2c";
278 reg = <0x50280000 0x100>;
282 clock-names = "ref", "pclk";
287 compatible = "snps,designware-i2c";
288 reg = <0x50290000 0x100>;
292 clock-names = "ref", "pclk";
297 compatible = "snps,designware-i2c";
298 reg = <0x502A0000 0x100>;
302 clock-names = "ref", "pclk";
307 compatible = "canaan,k210-fpioa";
308 reg = <0x502B0000 0x100>;
311 clock-names = "ref", "pclk";
313 canaan,k210-sysctl-power = <&sysctl 108>;
317 compatible = "snps,dw-apb-timer";
318 reg = <0x502D0000 0x100>;
322 clock-names = "timer", "pclk";
327 compatible = "snps,dw-apb-timer";
328 reg = <0x502E0000 0x100>;
332 clock-names = "timer", "pclk";
337 compatible = "snps,dw-apb-timer";
338 reg = <0x502F0000 0x100>;
342 clock-names = "timer", "pclk";
348 #address-cells = <1>;
349 #size-cells = <1>;
350 compatible = "simple-pm-bus";
355 compatible = "snps,dw-wdt";
356 reg = <0x50400000 0x100>;
360 clock-names = "tclk", "pclk";
365 compatible = "snps,dw-wdt";
366 reg = <0x50410000 0x100>;
370 clock-names = "tclk", "pclk";
375 compatible = "canaan,k210-sysctl",
376 "syscon", "simple-mfd";
377 reg = <0x50440000 0x100>;
379 clock-names = "pclk";
381 sysclk: clock-controller {
382 #clock-cells = <1>;
383 compatible = "canaan,k210-clk";
387 sysrst: reset-controller {
388 compatible = "canaan,k210-rst";
389 #reset-cells = <1>;
392 reboot: syscon-reboot {
393 compatible = "syscon-reboot";
403 #address-cells = <1>;
404 #size-cells = <1>;
405 compatible = "simple-pm-bus";
410 #address-cells = <1>;
411 #size-cells = <0>;
412 compatible = "canaan,k210-spi";
413 reg = <0x52000000 0x100>;
417 clock-names = "ssi_clk", "pclk";
419 reset-names = "spi";
420 spi-max-frequency = <25000000>;
421 num-cs = <4>;
422 reg-io-width = <4>;
426 #address-cells = <1>;
427 #size-cells = <0>;
428 compatible = "canaan,k210-spi";
429 reg = <0x53000000 0x100>;
433 clock-names = "ssi_clk", "pclk";
435 reset-names = "spi";
436 spi-max-frequency = <25000000>;
437 num-cs = <4>;
438 reg-io-width = <4>;
442 #address-cells = <1>;
443 #size-cells = <0>;
444 compatible = "snps,dwc-ssi-1.01a";
445 reg = <0x54000000 0x200>;
449 clock-names = "ssi_clk", "pclk";
451 reset-names = "spi";
453 spi-max-frequency = <100000000>;
454 num-cs = <4>;
455 reg-io-width = <4>;