43 #define DBG_VERBOSE(fmt...)	do { } while(0)
89  * or 0 if there is no new entry.
98 		return 0;  in xive_read_eq()
103 		return 0;  in xive_read_eq()
111 		if (q->idx == 0)  in xive_read_eq()
115 	return cur & 0x7fffffff;  in xive_read_eq()
125  * (0xff if none) and return what was found (0 if none).
141 static u32 xive_scan_interrupts(struct xive_cpu *xc, bool just_peek)  in xive_scan_interrupts()  argument
143 	u32 irq = 0;  in xive_scan_interrupts()
144 	u8 prio = 0;  in xive_scan_interrupts()
147 	while (xc->pending_prio != 0) {  in xive_scan_interrupts()
150 		prio = ffs(xc->pending_prio) - 1;  in xive_scan_interrupts()
154 		irq = xive_read_eq(&xc->queue[prio], just_peek);  in xive_scan_interrupts()
172 		xc->pending_prio &= ~(1 << prio);  in xive_scan_interrupts()
179 		q = &xc->queue[prio];  in xive_scan_interrupts()
181 			int p = atomic_xchg(&q->pending_count, 0);  in xive_scan_interrupts()
189 	/* If nothing was found, set CPPR to 0xff */  in xive_scan_interrupts()
190 	if (irq == 0)  in xive_scan_interrupts()
191 		prio = 0xff;  in xive_scan_interrupts()
194 	if (prio != xc->cppr) {  in xive_scan_interrupts()
196 		xc->cppr = prio;  in xive_scan_interrupts()
215 		val = xive_ops->esb_rw(xd->hw_irq, offset, 0, 0);  in xive_esb_read()
247 	struct xive_cpu *xc = per_cpu(xive_cpu, cpu);  in xmon_xive_do_dump()  local
250 	if (xc) {  in xmon_xive_do_dump()
251 		xmon_printf("pp=%02x CPPR=%02x ", xc->pending_prio, xc->cppr);  in xmon_xive_do_dump()
255 			u64 val = xive_esb_read(&xc->ipi_data, XIVE_ESB_GET);  in xmon_xive_do_dump()
257 			xmon_printf("IPI=0x%08x PQ=%c%c ", xc->hw_ipi,  in xmon_xive_do_dump()
262 		xive_dump_eq("EQ", &xc->queue[xive_irq_priority]);  in xmon_xive_do_dump()
283 		xmon_printf("IRQ 0x%08x : no config rc=%d\n", hw_irq, rc);  in xmon_xive_get_irq_config()
287 	xmon_printf("IRQ 0x%08x : target=0x%x prio=%02x lirq=0x%x ",  in xmon_xive_get_irq_config()
306 	return 0;  in xmon_xive_get_irq_config()
326 	struct xive_cpu *xc = __this_cpu_read(xive_cpu);  in xive_get_irq()  local
343 	xive_ops->update_pending(xc);  in xive_get_irq()
345 	DBG_VERBOSE("get_irq: pending=%02x\n", xc->pending_prio);  in xive_get_irq()
348 	irq = xive_scan_interrupts(xc, false);  in xive_get_irq()
350 	DBG_VERBOSE("get_irq: got irq 0x%x, new pending=0x%02x\n",  in xive_get_irq()
351 	    irq, xc->pending_prio);  in xive_get_irq()
355 		return 0;  in xive_get_irq()
369 static void xive_do_queue_eoi(struct xive_cpu *xc)  in xive_do_queue_eoi()  argument
371 	if (xive_scan_interrupts(xc, true) != 0) {  in xive_do_queue_eoi()
372 		DBG_VERBOSE("eoi: pending=0x%02x\n", xc->pending_prio);  in xive_do_queue_eoi()
389 		xive_esb_write(xd, XIVE_ESB_STORE_EOI, 0);  in xive_do_source_eoi()
414 		out_be64(xd->trig_mmio, 0);  in xive_do_source_eoi()
421 	struct xive_cpu *xc = __this_cpu_read(xive_cpu);  in xive_irq_eoi()  local
423 	DBG_VERBOSE("eoi_irq: irq=%d [0x%lx] pending=%02x\n",  in xive_irq_eoi()
424 		    d->irq, irqd_to_hwirq(d), xc->pending_prio);  in xive_irq_eoi()
443 	xive_do_queue_eoi(xc);  in xive_irq_eoi()
483 	struct xive_cpu *xc = per_cpu(xive_cpu, cpu);  in xive_try_pick_target()  local
484 	struct xive_q *q = &xc->queue[xive_irq_priority];  in xive_try_pick_target()
507 	struct xive_cpu *xc = per_cpu(xive_cpu, cpu);  in xive_dec_target_count()  local
508 	struct xive_q *q = &xc->queue[xive_irq_priority];  in xive_dec_target_count()
510 	if (WARN_ON(cpu < 0 || !xc)) {  in xive_dec_target_count()
511 		pr_err("%s: cpu=%d xc=%p\n", __func__, cpu, xc);  in xive_dec_target_count()
537 	for (i = 0; i < first && cpu < nr_cpu_ids; i++)  in xive_find_target_in_mask()
588 			struct xive_cpu *xc = per_cpu(xive_cpu, cpu);  in xive_pick_irq_target()  local
589 			if (xc->chip_id == xd->src_chip)  in xive_pick_irq_target()
598 		if (cpu >= 0)  in xive_pick_irq_target()
615 	pr_devel("xive_irq_startup: irq %d [0x%x] data @%p\n",  in xive_irq_startup()
648 	return 0;  in xive_irq_startup()
657 	pr_devel("xive_irq_shutdown: irq %d [0x%x] data @%p\n",  in xive_irq_shutdown()
672 				0xff, XIVE_BAD_IRQ);  in xive_irq_shutdown()
703 	int rc = 0;  in xive_irq_set_affinity()
741 	if (rc < 0) {  in xive_irq_set_affinity()
746 	pr_debug("  target: 0x%x\n", target);  in xive_irq_set_affinity()
786 		pr_warn("Interrupt %d (HW 0x%x) type mismatch, Linux says %s, FW says %s\n",  in xive_irq_set_type()
801 		return 0;  in xive_irq_retrigger()
846 			return 0;  in xive_irq_set_vcpu_affinity()
885 			return 0;  in xive_irq_set_vcpu_affinity()
926 	return 0;  in xive_irq_set_vcpu_affinity()
950 		return 0;  in xive_get_irqchip_state()
1018 	return 0;  in xive_irq_alloc_data()
1037 	struct xive_cpu *xc;  in xive_cause_ipi()  local
1040 	xc = per_cpu(xive_cpu, cpu);  in xive_cause_ipi()
1042 	DBG_VERBOSE("IPI CPU %d -> %d (HW IRQ 0x%x)\n",  in xive_cause_ipi()
1043 		    smp_processor_id(), cpu, xc->hw_ipi);  in xive_cause_ipi()
1045 	xd = &xc->ipi_data;  in xive_cause_ipi()
1048 	out_be64(xd->trig_mmio, 0);  in xive_cause_ipi()
1058 	struct xive_cpu *xc = __this_cpu_read(xive_cpu);  in xive_ipi_eoi()  local
1061 	if (!xc)  in xive_ipi_eoi()
1064 	DBG_VERBOSE("IPI eoi: irq=%d [0x%lx] (HW IRQ 0x%x) pending=%02x\n",  in xive_ipi_eoi()
1065 		    d->irq, irqd_to_hwirq(d), xc->hw_ipi, xc->pending_prio);  in xive_ipi_eoi()
1067 	xive_do_source_eoi(&xc->ipi_data);  in xive_ipi_eoi()
1068 	xive_do_queue_eoi(xc);  in xive_ipi_eoi()
1100 	for (i = 0; i < nr_irqs; i++) {  in xive_ipi_irq_domain_alloc()
1105 	return 0;  in xive_ipi_irq_domain_alloc()
1142 		if (ret < 0)  in xive_init_ipis()
1167 		return 0;  in xive_request_ipi()
1173 	WARN(ret < 0, "Failed to request IPI %d: %d\n", xid->irq, ret);  in xive_request_ipi()
1180 	struct xive_cpu *xc;  in xive_setup_cpu_ipi()  local
1185 	xc = per_cpu(xive_cpu, cpu);  in xive_setup_cpu_ipi()
1188 	if (xc->hw_ipi != XIVE_BAD_IRQ)  in xive_setup_cpu_ipi()
1189 		return 0;  in xive_setup_cpu_ipi()
1194 	/* Grab an IPI from the backend, this will populate xc->hw_ipi */  in xive_setup_cpu_ipi()
1195 	if (xive_ops->get_ipi(cpu, xc))  in xive_setup_cpu_ipi()
1202 	rc = xive_ops->populate_irq_data(xc->hw_ipi, &xc->ipi_data);  in xive_setup_cpu_ipi()
1207 	rc = xive_ops->configure_irq(xc->hw_ipi,  in xive_setup_cpu_ipi()
1215 	    xc->hw_ipi, xive_ipi_irq, xc->ipi_data.trig_mmio);  in xive_setup_cpu_ipi()
1218 	xive_do_source_set_mask(&xc->ipi_data, false);  in xive_setup_cpu_ipi()
1220 	return 0;  in xive_setup_cpu_ipi()
1223 static void xive_cleanup_cpu_ipi(unsigned int cpu, struct xive_cpu *xc)  in xive_cleanup_cpu_ipi()  argument
1230 	if (xc->hw_ipi == XIVE_BAD_IRQ)  in xive_cleanup_cpu_ipi()
1236 	xive_do_source_set_mask(&xc->ipi_data, true);  in xive_cleanup_cpu_ipi()
1245 	xive_ops->configure_irq(xc->hw_ipi, hard_smp_processor_id(),  in xive_cleanup_cpu_ipi()
1246 				0xff, xive_ipi_irq);  in xive_cleanup_cpu_ipi()
1249 	xive_ops->put_ipi(cpu, xc);  in xive_cleanup_cpu_ipi()
1282 	return 0;  in xive_irq_domain_map()
1295 	*out_hwirq = intspec[0];  in xive_irq_domain_xlate()
1309 	return 0;  in xive_irq_domain_xlate()
1355 	seq_printf(m, "%*sESB:      %s\n", ind, "", esb_names[val & 0x3]);  in xive_irq_domain_debug_show()
1360 	seq_printf(m, "%*sTrigger:  0x%016llx\n", ind, "", xd->trig_page);  in xive_irq_domain_debug_show()
1361 	seq_printf(m, "%*sEOI:      0x%016llx\n", ind, "", xd->eoi_page);  in xive_irq_domain_debug_show()
1362 	seq_printf(m, "%*sFlags:    0x%llx\n", ind, "", xd->flags);  in xive_irq_domain_debug_show()
1363 	for (i = 0; i < ARRAY_SIZE(xive_irq_flags); i++) {  in xive_irq_domain_debug_show()
1395 	for (i = 0; i < nr_irqs; i++) {  in xive_irq_domain_alloc()
1414 	return 0;  in xive_irq_domain_alloc()
1424 	for (i = 0; i < nr_irqs; i++)  in xive_irq_domain_free()
1453 static void xive_cleanup_cpu_queues(unsigned int cpu, struct xive_cpu *xc)  in xive_cleanup_cpu_queues()  argument
1455 	if (xc->queue[xive_irq_priority].qpage)  in xive_cleanup_cpu_queues()
1456 		xive_ops->cleanup_queue(cpu, xc, xive_irq_priority);  in xive_cleanup_cpu_queues()
1459 static int xive_setup_cpu_queues(unsigned int cpu, struct xive_cpu *xc)  in xive_setup_cpu_queues()  argument
1461 	int rc = 0;  in xive_setup_cpu_queues()
1464 	if (!xc->queue[xive_irq_priority].qpage)  in xive_setup_cpu_queues()
1465 		rc = xive_ops->setup_queue(cpu, xc, xive_irq_priority);  in xive_setup_cpu_queues()
1472 	struct xive_cpu *xc;  in xive_prepare_cpu()  local
1474 	xc = per_cpu(xive_cpu, cpu);  in xive_prepare_cpu()
1475 	if (!xc) {  in xive_prepare_cpu()
1476 		xc = kzalloc_node(sizeof(struct xive_cpu),  in xive_prepare_cpu()
1478 		if (!xc)  in xive_prepare_cpu()
1480 		xc->hw_ipi = XIVE_BAD_IRQ;  in xive_prepare_cpu()
1481 		xc->chip_id = XIVE_INVALID_CHIP_ID;  in xive_prepare_cpu()
1483 			xive_ops->prepare_cpu(cpu, xc);  in xive_prepare_cpu()
1485 		per_cpu(xive_cpu, cpu) = xc;  in xive_prepare_cpu()
1489 	return xive_setup_cpu_queues(cpu, xc);  in xive_prepare_cpu()
1494 	struct xive_cpu *xc = __this_cpu_read(xive_cpu);  in xive_setup_cpu()  local
1498 		xive_ops->setup_cpu(smp_processor_id(), xc);  in xive_setup_cpu()
1500 	/* Set CPPR to 0xff to enable flow of interrupts */  in xive_setup_cpu()
1501 	xc->cppr = 0xff;  in xive_setup_cpu()
1502 	out_8(xive_tima + xive_tima_offset + TM_CPPR, 0xff);  in xive_setup_cpu()
1530 static void xive_flush_cpu_queue(unsigned int cpu, struct xive_cpu *xc)  in xive_flush_cpu_queue()  argument
1538 	while ((irq = xive_scan_interrupts(xc, false)) != 0) {  in xive_flush_cpu_queue()
1586 	struct xive_cpu *xc = __this_cpu_read(xive_cpu);  in xive_smp_disable_cpu()  local
1592 	/* Set CPPR to 0 to disable flow of interrupts */  in xive_smp_disable_cpu()
1593 	xc->cppr = 0;  in xive_smp_disable_cpu()
1594 	out_8(xive_tima + xive_tima_offset + TM_CPPR, 0);  in xive_smp_disable_cpu()
1597 	xive_flush_cpu_queue(cpu, xc);  in xive_smp_disable_cpu()
1600 	xc->cppr = 0xff;  in xive_smp_disable_cpu()
1601 	out_8(xive_tima + xive_tima_offset + TM_CPPR, 0xff);  in xive_smp_disable_cpu()
1606 	struct xive_cpu *xc = __this_cpu_read(xive_cpu);  in xive_flush_interrupt()  local
1610 	xive_flush_cpu_queue(cpu, xc);  in xive_flush_interrupt()
1619 	struct xive_cpu *xc = __this_cpu_read(xive_cpu);  in xive_teardown_cpu()  local
1622 	/* Set CPPR to 0 to disable flow of interrupts */  in xive_teardown_cpu()
1623 	xc->cppr = 0;  in xive_teardown_cpu()
1624 	out_8(xive_tima + xive_tima_offset + TM_CPPR, 0);  in xive_teardown_cpu()
1627 		xive_ops->teardown_cpu(cpu, xc);  in xive_teardown_cpu()
1631 	xive_cleanup_cpu_ipi(cpu, xc);  in xive_teardown_cpu()
1635 	xive_cleanup_cpu_queues(cpu, xc);  in xive_teardown_cpu()
1683 	memset(qpage, 0, 1 << queue_shift);  in xive_queue_page_alloc()
1691 	return 0;  in xive_off()
1697 	struct xive_cpu *xc = per_cpu(xive_cpu, cpu);  in xive_debug_show_cpu()  local
1700 	if (xc) {  in xive_debug_show_cpu()
1701 		seq_printf(m, "pp=%02x CPPR=%02x ", xc->pending_prio, xc->cppr);  in xive_debug_show_cpu()
1705 			u64 val = xive_esb_read(&xc->ipi_data, XIVE_ESB_GET);  in xive_debug_show_cpu()
1707 			seq_printf(m, "IPI=0x%08x PQ=%c%c ", xc->hw_ipi,  in xive_debug_show_cpu()
1713 			struct xive_q *q = &xc->queue[xive_irq_priority];  in xive_debug_show_cpu()
1741 		seq_printf(m, "IRQ 0x%08x : no config rc=%d\n", hw_irq, rc);  in xive_debug_show_irq()
1745 	seq_printf(m, "IRQ 0x%08x : target=0x%x prio=%02x lirq=0x%x ",  in xive_debug_show_irq()
1777 	return 0;  in xive_core_debug_show()
1786 	return 0;  in xive_core_debug_init()