Lines Matching +full:1 +full:c
39 * MMCR1[25] = pmc1combine[1]
41 * MMCR1[27] = pmc2combine[1]
43 * MMCR1[29] = pmc3combine[1]
45 * MMCR1[31] = pmc4combine[1]
61 * MMCR1[17] = cache_sel[1]
65 * MMCRA[63] = 1 (SAMPLE_ENABLE)
72 * MMCRA[SDAR_MODE] = sdar_mode[0:1]
308 return -1; in power10_bhrb_filter_map()
321 return -1; in power10_bhrb_filter_map()
329 return -1; in power10_bhrb_filter_map()
340 #define C(x) PERF_COUNT_HW_CACHE_##x macro
344 * 0 means not supported, -1 means nonsensical, other values
347 static u64 power10_cache_events_dd1[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
348 [C(L1D)] = {
349 [C(OP_READ)] = {
350 [C(RESULT_ACCESS)] = PM_LD_REF_L1,
351 [C(RESULT_MISS)] = PM_LD_MISS_L1,
353 [C(OP_WRITE)] = {
354 [C(RESULT_ACCESS)] = 0,
355 [C(RESULT_MISS)] = PM_ST_MISS_L1,
357 [C(OP_PREFETCH)] = {
358 [C(RESULT_ACCESS)] = PM_LD_PREFETCH_CACHE_LINE_MISS,
359 [C(RESULT_MISS)] = 0,
362 [C(L1I)] = {
363 [C(OP_READ)] = {
364 [C(RESULT_ACCESS)] = PM_INST_FROM_L1,
365 [C(RESULT_MISS)] = PM_L1_ICACHE_MISS,
367 [C(OP_WRITE)] = {
368 [C(RESULT_ACCESS)] = PM_INST_FROM_L1MISS,
369 [C(RESULT_MISS)] = -1,
371 [C(OP_PREFETCH)] = {
372 [C(RESULT_ACCESS)] = PM_IC_PREF_REQ,
373 [C(RESULT_MISS)] = 0,
376 [C(LL)] = {
377 [C(OP_READ)] = {
378 [C(RESULT_ACCESS)] = PM_DATA_FROM_L3,
379 [C(RESULT_MISS)] = PM_DATA_FROM_L3MISS,
381 [C(OP_WRITE)] = {
382 [C(RESULT_ACCESS)] = -1,
383 [C(RESULT_MISS)] = -1,
385 [C(OP_PREFETCH)] = {
386 [C(RESULT_ACCESS)] = -1,
387 [C(RESULT_MISS)] = 0,
390 [C(DTLB)] = {
391 [C(OP_READ)] = {
392 [C(RESULT_ACCESS)] = 0,
393 [C(RESULT_MISS)] = PM_DTLB_MISS,
395 [C(OP_WRITE)] = {
396 [C(RESULT_ACCESS)] = -1,
397 [C(RESULT_MISS)] = -1,
399 [C(OP_PREFETCH)] = {
400 [C(RESULT_ACCESS)] = -1,
401 [C(RESULT_MISS)] = -1,
404 [C(ITLB)] = {
405 [C(OP_READ)] = {
406 [C(RESULT_ACCESS)] = 0,
407 [C(RESULT_MISS)] = PM_ITLB_MISS,
409 [C(OP_WRITE)] = {
410 [C(RESULT_ACCESS)] = -1,
411 [C(RESULT_MISS)] = -1,
413 [C(OP_PREFETCH)] = {
414 [C(RESULT_ACCESS)] = -1,
415 [C(RESULT_MISS)] = -1,
418 [C(BPU)] = {
419 [C(OP_READ)] = {
420 [C(RESULT_ACCESS)] = PM_BR_CMPL,
421 [C(RESULT_MISS)] = PM_BR_MPRED_CMPL,
423 [C(OP_WRITE)] = {
424 [C(RESULT_ACCESS)] = -1,
425 [C(RESULT_MISS)] = -1,
427 [C(OP_PREFETCH)] = {
428 [C(RESULT_ACCESS)] = -1,
429 [C(RESULT_MISS)] = -1,
432 [C(NODE)] = {
433 [C(OP_READ)] = {
434 [C(RESULT_ACCESS)] = -1,
435 [C(RESULT_MISS)] = -1,
437 [C(OP_WRITE)] = {
438 [C(RESULT_ACCESS)] = -1,
439 [C(RESULT_MISS)] = -1,
441 [C(OP_PREFETCH)] = {
442 [C(RESULT_ACCESS)] = -1,
443 [C(RESULT_MISS)] = -1,
448 static u64 power10_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
449 [C(L1D)] = {
450 [C(OP_READ)] = {
451 [C(RESULT_ACCESS)] = PM_LD_REF_L1,
452 [C(RESULT_MISS)] = PM_LD_MISS_L1,
454 [C(OP_WRITE)] = {
455 [C(RESULT_ACCESS)] = 0,
456 [C(RESULT_MISS)] = PM_ST_MISS_L1,
458 [C(OP_PREFETCH)] = {
459 [C(RESULT_ACCESS)] = PM_LD_PREFETCH_CACHE_LINE_MISS,
460 [C(RESULT_MISS)] = 0,
463 [C(L1I)] = {
464 [C(OP_READ)] = {
465 [C(RESULT_ACCESS)] = PM_INST_FROM_L1,
466 [C(RESULT_MISS)] = PM_L1_ICACHE_MISS,
468 [C(OP_WRITE)] = {
469 [C(RESULT_ACCESS)] = PM_INST_FROM_L1MISS,
470 [C(RESULT_MISS)] = -1,
472 [C(OP_PREFETCH)] = {
473 [C(RESULT_ACCESS)] = PM_IC_PREF_REQ,
474 [C(RESULT_MISS)] = 0,
477 [C(LL)] = {
478 [C(OP_READ)] = {
479 [C(RESULT_ACCESS)] = PM_DATA_FROM_L3,
480 [C(RESULT_MISS)] = PM_DATA_FROM_L3MISS,
482 [C(OP_WRITE)] = {
483 [C(RESULT_ACCESS)] = PM_L2_ST,
484 [C(RESULT_MISS)] = PM_L2_ST_MISS,
486 [C(OP_PREFETCH)] = {
487 [C(RESULT_ACCESS)] = PM_L3_PF_MISS_L3,
488 [C(RESULT_MISS)] = 0,
491 [C(DTLB)] = {
492 [C(OP_READ)] = {
493 [C(RESULT_ACCESS)] = 0,
494 [C(RESULT_MISS)] = PM_DTLB_MISS,
496 [C(OP_WRITE)] = {
497 [C(RESULT_ACCESS)] = -1,
498 [C(RESULT_MISS)] = -1,
500 [C(OP_PREFETCH)] = {
501 [C(RESULT_ACCESS)] = -1,
502 [C(RESULT_MISS)] = -1,
505 [C(ITLB)] = {
506 [C(OP_READ)] = {
507 [C(RESULT_ACCESS)] = 0,
508 [C(RESULT_MISS)] = PM_ITLB_MISS,
510 [C(OP_WRITE)] = {
511 [C(RESULT_ACCESS)] = -1,
512 [C(RESULT_MISS)] = -1,
514 [C(OP_PREFETCH)] = {
515 [C(RESULT_ACCESS)] = -1,
516 [C(RESULT_MISS)] = -1,
519 [C(BPU)] = {
520 [C(OP_READ)] = {
521 [C(RESULT_ACCESS)] = PM_BR_CMPL,
522 [C(RESULT_MISS)] = PM_BR_MPRED_CMPL,
524 [C(OP_WRITE)] = {
525 [C(RESULT_ACCESS)] = -1,
526 [C(RESULT_MISS)] = -1,
528 [C(OP_PREFETCH)] = {
529 [C(RESULT_ACCESS)] = -1,
530 [C(RESULT_MISS)] = -1,
533 [C(NODE)] = {
534 [C(OP_READ)] = {
535 [C(RESULT_ACCESS)] = -1,
536 [C(RESULT_MISS)] = -1,
538 [C(OP_WRITE)] = {
539 [C(RESULT_ACCESS)] = -1,
540 [C(RESULT_MISS)] = -1,
542 [C(OP_PREFETCH)] = {
543 [C(RESULT_ACCESS)] = -1,
544 [C(RESULT_MISS)] = -1,
549 #undef C
589 if ((PVR_CFG(pvr) == 1)) in init_power10_pmu()
595 if ((PVR_CFG(pvr) == 1)) { in init_power10_pmu()