Lines Matching +full:tlb +full:- +full:split
1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
30 * Table of generalized cache-related events.
31 * 0 means not supported, -1 means nonsensical, other values
36 * D-cache misses are not split into read/write/prefetch;
46 [C(OP_WRITE)] = { -1, -1 },
62 * the chip's internal level-one TLB which is probably not
63 * what the user wants. Instead, unified level-two TLB misses
68 [C(OP_WRITE)] = { -1, -1 },
69 [C(OP_PREFETCH)] = { -1, -1 },
73 [C(OP_WRITE)] = { -1, -1 },
74 [C(OP_PREFETCH)] = { -1, -1 },
77 [C(OP_READ)] = { -1, -1 },
78 [C(OP_WRITE)] = { -1, -1 },
79 [C(OP_PREFETCH)] = { -1, -1 },
102 /* Threshold requested on non-threshold event */ in e500_xlate_event()
121 if (!cur_cpu_spec->oprofile_cpu_type) in init_e500_pmu()
122 return -ENODEV; in init_e500_pmu()
124 if (!strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc/e500mc")) in init_e500_pmu()
126 else if (strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc/e500")) in init_e500_pmu()
127 return -ENODEV; in init_e500_pmu()