Lines Matching +full:y +full:- +full:rp
1 // SPDX-License-Identifier: GPL-2.0-or-later
12 * Common pmac/prep/chrp pci routines. -- Cort
37 #include <asm/pci-bridge.h>
40 #include <asm/ppc-pci.h>
76 int ret, phb_id = -1; in get_phb_number()
82 * the respective device-tree properties. Firstly, try powernv by in get_phb_number()
83 * reading "ibm,opal-phbid", only present in OPAL environment. in get_phb_number()
85 ret = of_property_read_u64(dn, "ibm,opal-phbid", &prop); in get_phb_number()
92 phb_id = (int)(prop & (MAX_PHBS - 1)); in get_phb_number()
117 phb->global_number = get_phb_number(dev); in pcibios_alloc_controller()
118 list_add_tail(&phb->list_node, &hose_list); in pcibios_alloc_controller()
120 phb->dn = dev; in pcibios_alloc_controller()
121 phb->is_dynamic = slab_is_available(); in pcibios_alloc_controller()
141 if (phb->global_number < MAX_PHBS) in pcibios_free_controller()
142 clear_bit(phb->global_number, phb_bitmap); in pcibios_free_controller()
144 list_del(&phb->list_node); in pcibios_free_controller()
147 if (phb->is_dynamic) in pcibios_free_controller()
164 * (root bus) - it expects .release_data to hold a pointer
180 bridge->release_data; in pcibios_free_controller_deferred()
182 pr_debug("domain %d, dynamic %d\n", phb->global_number, phb->is_dynamic); in pcibios_free_controller_deferred()
199 if (phb->controller_ops.window_alignment) in pcibios_window_alignment()
200 return phb->controller_ops.window_alignment(bus, type); in pcibios_window_alignment()
214 if (hose->controller_ops.setup_bridge) in pcibios_setup_bridge()
215 hose->controller_ops.setup_bridge(bus, type); in pcibios_setup_bridge()
220 struct pci_controller *phb = pci_bus_to_host(dev->bus); in pcibios_reset_secondary_bus()
222 if (phb->controller_ops.reset_secondary_bus) { in pcibios_reset_secondary_bus()
223 phb->controller_ops.reset_secondary_bus(dev); in pcibios_reset_secondary_bus()
268 return hose->pci_io_size; in pcibios_io_size()
270 return resource_size(&hose->io_resource); in pcibios_io_size()
283 if (address >= hose->io_base_virt && in pcibios_vaddr_is_ioport()
284 address < (hose->io_base_virt + size)) { in pcibios_vaddr_is_ioport()
302 if (address >= hose->io_base_phys && in pci_address_to_pio()
303 address < (hose->io_base_phys + size)) { in pci_address_to_pio()
305 (unsigned long)hose->io_base_virt - _IO_BASE; in pci_address_to_pio()
306 ret = base + (address - hose->io_base_phys); in pci_address_to_pio()
323 return hose->global_number; in pci_domain_nr()
339 if (hose->dn == node) in pci_find_hose_for_OF_device()
341 node = node->parent; in pci_find_hose_for_OF_device()
351 if (hose->global_number == domain_nr) in pci_find_controller_for_domain()
370 list_del(&vi->list_node); in ppc_pci_intx_release()
371 irq_dispose_mapping(vi->virq); in ppc_pci_intx_release()
385 if (vi->virq == pdev->irq) { in ppc_pci_unmap_irq_line()
386 kref_put(&vi->kref, ppc_pci_intx_release); in ppc_pci_unmap_irq_line()
419 return -1; in pci_read_irq_line()
423 /* Try to get a mapping from the device-tree */ in pci_read_irq_line()
458 pci_dev->irq = virq; in pci_read_irq_line()
462 if (vitmp->virq == virq) { in pci_read_irq_line()
463 kref_get(&vitmp->kref); in pci_read_irq_line()
470 vi->virq = virq; in pci_read_irq_line()
471 kref_init(&vi->kref); in pci_read_irq_line()
472 list_add_tail(&vi->list_node, &intx_list); in pci_read_irq_line()
479 return -1; in pci_read_irq_line()
483 * Platform support for /proc/bus/pci/X/Y mmap()s.
484 * -- paulus.
488 struct pci_controller *hose = pci_bus_to_host(pdev->bus); in pci_iobar_pfn()
492 return -EINVAL; in pci_iobar_pfn()
495 ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE; in pci_iobar_pfn()
497 vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT; in pci_iobar_pfn()
522 struct resource *rp = &pdev->resource[i]; in pci_phys_mem_access_prot() local
523 int flags = rp->flags; in pci_phys_mem_access_prot()
529 if (offset < (rp->start & PAGE_MASK) || in pci_phys_mem_access_prot()
530 offset > rp->end) in pci_phys_mem_access_prot()
532 found = rp; in pci_phys_mem_access_prot()
539 if (found->flags & IORESOURCE_PREFETCH) in pci_phys_mem_access_prot()
544 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n", in pci_phys_mem_access_prot()
555 struct resource *rp = &hose->io_resource; in pci_legacy_read() local
563 offset = (unsigned long)hose->io_base_virt - _IO_BASE; in pci_legacy_read()
566 if (!(rp->flags & IORESOURCE_IO)) in pci_legacy_read()
567 return -ENXIO; in pci_legacy_read()
568 if (offset < rp->start || (offset + size) > rp->end) in pci_legacy_read()
569 return -ENXIO; in pci_legacy_read()
570 addr = hose->io_base_virt + port; in pci_legacy_read()
578 return -EINVAL; in pci_legacy_read()
583 return -EINVAL; in pci_legacy_read()
587 return -EINVAL; in pci_legacy_read()
595 struct resource *rp = &hose->io_resource; in pci_legacy_write() local
603 offset = (unsigned long)hose->io_base_virt - _IO_BASE; in pci_legacy_write()
606 if (!(rp->flags & IORESOURCE_IO)) in pci_legacy_write()
607 return -ENXIO; in pci_legacy_write()
608 if (offset < rp->start || (offset + size) > rp->end) in pci_legacy_write()
609 return -ENXIO; in pci_legacy_write()
610 addr = hose->io_base_virt + port; in pci_legacy_write()
623 return -EINVAL; in pci_legacy_write()
628 return -EINVAL; in pci_legacy_write()
632 return -EINVAL; in pci_legacy_write()
642 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; in pci_mmap_legacy_page_range()
643 resource_size_t size = vma->vm_end - vma->vm_start; in pci_mmap_legacy_page_range()
644 struct resource *rp; in pci_mmap_legacy_page_range() local
647 pci_domain_nr(bus), bus->number, in pci_mmap_legacy_page_range()
650 (unsigned long long)(offset + size - 1)); in pci_mmap_legacy_page_range()
660 if ((offset + size) > hose->isa_mem_size) { in pci_mmap_legacy_page_range()
662 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n", in pci_mmap_legacy_page_range()
663 current->comm, current->pid, pci_domain_nr(bus), bus->number); in pci_mmap_legacy_page_range()
664 if (vma->vm_flags & VM_SHARED) in pci_mmap_legacy_page_range()
668 offset += hose->isa_mem_phys; in pci_mmap_legacy_page_range()
670 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; in pci_mmap_legacy_page_range()
672 rp = &hose->io_resource; in pci_mmap_legacy_page_range()
673 if (!(rp->flags & IORESOURCE_IO)) in pci_mmap_legacy_page_range()
674 return -ENXIO; in pci_mmap_legacy_page_range()
675 if (roffset < rp->start || (roffset + size) > rp->end) in pci_mmap_legacy_page_range()
676 return -ENXIO; in pci_mmap_legacy_page_range()
677 offset += hose->io_base_phys; in pci_mmap_legacy_page_range()
679 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset); in pci_mmap_legacy_page_range()
681 vma->vm_pgoff = offset >> PAGE_SHIFT; in pci_mmap_legacy_page_range()
682 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); in pci_mmap_legacy_page_range()
683 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, in pci_mmap_legacy_page_range()
684 vma->vm_end - vma->vm_start, in pci_mmap_legacy_page_range()
685 vma->vm_page_prot); in pci_mmap_legacy_page_range()
694 if (rsrc->flags & IORESOURCE_IO) { in pci_resource_to_user()
695 pcibios_resource_to_bus(dev->bus, ®ion, in pci_resource_to_user()
706 * That means we may have 64-bit values where some apps only expect in pci_resource_to_user()
707 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO). in pci_resource_to_user()
709 *start = rsrc->start; in pci_resource_to_user()
710 *end = rsrc->end; in pci_resource_to_user()
714 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
726 * - We can only cope with one IO space range and up to 3 Memory space
730 * - Some busses have IO space not starting at 0, which causes trouble with
734 * - Some 32 bits platforms such as 4xx can have physical space larger than
754 /* If we failed translation or got a zero-sized region in pci_process_bridge_OF_ranges()
767 " IO 0x%016llx..0x%016llx -> 0x%016llx\n", in pci_process_bridge_OF_ranges()
768 range.cpu_addr, range.cpu_addr + range.size - 1, in pci_process_bridge_OF_ranges()
772 if (hose->pci_io_size) { in pci_process_bridge_OF_ranges()
774 " \\--> Skipped (too many) !\n"); in pci_process_bridge_OF_ranges()
783 hose->io_base_virt = ioremap(range.cpu_addr, in pci_process_bridge_OF_ranges()
789 (unsigned long)hose->io_base_virt; in pci_process_bridge_OF_ranges()
794 hose->pci_io_size = range.pci_addr + range.size; in pci_process_bridge_OF_ranges()
795 hose->io_base_phys = range.cpu_addr - range.pci_addr; in pci_process_bridge_OF_ranges()
798 res = &hose->io_resource; in pci_process_bridge_OF_ranges()
803 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", in pci_process_bridge_OF_ranges()
804 range.cpu_addr, range.cpu_addr + range.size - 1, in pci_process_bridge_OF_ranges()
812 " \\--> Skipped (too many) !\n"); in pci_process_bridge_OF_ranges()
819 hose->isa_mem_phys = range.cpu_addr; in pci_process_bridge_OF_ranges()
820 hose->isa_mem_size = range.size; in pci_process_bridge_OF_ranges()
824 hose->mem_offset[memno] = range.cpu_addr - in pci_process_bridge_OF_ranges()
826 res = &hose->mem_resources[memno++]; in pci_process_bridge_OF_ranges()
830 res->name = dev->full_name; in pci_process_bridge_OF_ranges()
831 res->flags = range.flags; in pci_process_bridge_OF_ranges()
832 res->start = range.cpu_addr; in pci_process_bridge_OF_ranges()
833 res->end = range.cpu_addr + range.size - 1; in pci_process_bridge_OF_ranges()
834 res->parent = res->child = res->sibling = NULL; in pci_process_bridge_OF_ranges()
847 return hose->global_number != 0; in pci_proc_domain()
864 struct pci_controller *hose = pci_bus_to_host(dev->bus); in pcibios_fixup_resources()
873 if (dev->is_virtfn) in pcibios_fixup_resources()
877 struct resource *res = dev->resource + i; in pcibios_fixup_resources()
879 if (!res->flags) in pcibios_fixup_resources()
882 /* If we're going to re-assign everything, we mark all resources in pcibios_fixup_resources()
883 * as unset (and 0-base them). In addition, we mark BARs starting in pcibios_fixup_resources()
885 * since in that case, we don't want to re-assign anything in pcibios_fixup_resources()
887 pcibios_resource_to_bus(dev->bus, ®, res); in pcibios_fixup_resources()
890 /* Only print message if not re-assigning */ in pcibios_fixup_resources()
894 res->end -= res->start; in pcibios_fixup_resources()
895 res->start = 0; in pcibios_fixup_resources()
896 res->flags |= IORESOURCE_UNSET; in pcibios_fixup_resources()
912 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
918 struct pci_dev *dev = bus->self; in pcibios_uninitialized_bridge_resource()
929 if (res->flags & IORESOURCE_MEM) { in pcibios_uninitialized_bridge_resource()
930 pcibios_resource_to_bus(dev->bus, ®ion, res); in pcibios_uninitialized_bridge_resource()
932 /* If the BAR is non-0 then it's probably been initialized */ in pcibios_uninitialized_bridge_resource()
948 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) && in pcibios_uninitialized_bridge_resource()
949 hose->mem_resources[i].start == hose->mem_offset[i]) in pcibios_uninitialized_bridge_resource()
958 /* If the BAR is non-0, then we consider it assigned */ in pcibios_uninitialized_bridge_resource()
959 offset = (unsigned long)hose->io_base_virt - _IO_BASE; in pcibios_uninitialized_bridge_resource()
960 if (((res->start - offset) & 0xfffffffful) != 0) in pcibios_uninitialized_bridge_resource()
964 * starting at low addresses -is- valid. What we do instead if that in pcibios_uninitialized_bridge_resource()
979 /* Fixup resources of a PCI<->PCI bridge */
985 struct pci_dev *dev = bus->self; in pcibios_fixup_bridge()
988 if (!res || !res->flags) in pcibios_fixup_bridge()
990 if (i >= 3 && bus->self->transparent) in pcibios_fixup_bridge()
998 res->flags |= IORESOURCE_UNSET; in pcibios_fixup_bridge()
999 res->start = 0; in pcibios_fixup_bridge()
1000 res->end = -1; in pcibios_fixup_bridge()
1007 * and clear them out so they get re-assigned later in pcibios_fixup_bridge()
1010 res->flags = 0; in pcibios_fixup_bridge()
1021 if (bus->self != NULL) in pcibios_setup_bus_self()
1032 if (phb->controller_ops.dma_bus_setup) in pcibios_setup_bus_self()
1033 phb->controller_ops.dma_bus_setup(bus); in pcibios_setup_bus_self()
1042 set_dev_node(&dev->dev, pcibus_to_node(dev->bus)); in pcibios_bus_add_device()
1045 set_dma_ops(&dev->dev, pci_dma_ops); in pcibios_bus_add_device()
1046 dev->dev.archdata.dma_offset = PCI_DRAM_OFFSET; in pcibios_bus_add_device()
1049 phb = pci_bus_to_host(dev->bus); in pcibios_bus_add_device()
1050 if (phb->controller_ops.dma_dev_setup) in pcibios_bus_add_device()
1051 phb->controller_ops.dma_dev_setup(dev); in pcibios_bus_add_device()
1071 d = dev_get_msi_domain(&dev->bus->dev); in pcibios_add_device()
1073 dev_set_msi_domain(&dev->dev, d); in pcibios_add_device()
1084 /* When called from the generic PCI probe, read PCI<->PCI bridge in pcibios_fixup_bus()
1085 * bases. This is -not- called when generating the PCI tree from in pcibios_fixup_bus()
1086 * the OF device-tree. in pcibios_fixup_bus()
1098 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) in skip_isa_ioresource_align()
1106 * addresses to be allocated in the 0x000-0x0ff region
1110 * the low 10 bits of the IO address. The 0x00-0xff region
1112 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1113 * but we want to try to avoid allocating at 0x2900-0x2bff
1114 * which might have be mirrored at 0x0100-0x03ff..
1120 resource_size_t start = res->start; in pcibios_align_resource()
1122 if (res->flags & IORESOURCE_IO) { in pcibios_align_resource()
1143 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { in reparent_resources()
1144 if (p->end < res->start) in reparent_resources()
1146 if (res->end < p->start) in reparent_resources()
1148 if (p->start < res->start || p->end > res->end) in reparent_resources()
1149 return -1; /* not completely contained */ in reparent_resources()
1154 return -1; /* didn't find any conflicting entries? */ in reparent_resources()
1155 res->parent = parent; in reparent_resources()
1156 res->child = *firstpp; in reparent_resources()
1157 res->sibling = *pp; in reparent_resources()
1160 for (p = res->child; p != NULL; p = p->sibling) { in reparent_resources()
1161 p->parent = res; in reparent_resources()
1163 p->name, p, res->name); in reparent_resources()
1171 * On the other hand, we cannot just re-allocate all devices, as it would
1177 * - I/O or memory regions not configured
1178 * - regions configured, but not enabled in the command register
1179 * - bogus I/O addresses above 64K used
1180 * - expansion ROMs left enabled (this may sound harmless, but given
1186 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1208 pci_domain_nr(bus), bus->number); in pcibios_allocate_bus_resources()
1211 if (!res || !res->flags || res->start > res->end || res->parent) in pcibios_allocate_bus_resources()
1215 if (res->flags & IORESOURCE_UNSET) in pcibios_allocate_bus_resources()
1218 if (bus->parent == NULL) in pcibios_allocate_bus_resources()
1219 pr = (res->flags & IORESOURCE_IO) ? in pcibios_allocate_bus_resources()
1222 pr = pci_find_parent_resource(bus->self, res); in pcibios_allocate_bus_resources()
1226 * bridge is transparent -- paulus in pcibios_allocate_bus_resources()
1233 bus->self ? pci_name(bus->self) : "PHB", bus->number, in pcibios_allocate_bus_resources()
1234 i, res, pr, (pr && pr->name) ? pr->name : "nil"); in pcibios_allocate_bus_resources()
1236 if (pr && !(pr->flags & IORESOURCE_UNSET)) { in pcibios_allocate_bus_resources()
1237 struct pci_dev *dev = bus->self; in pcibios_allocate_bus_resources()
1255 i, bus->number); in pcibios_allocate_bus_resources()
1263 res->start = 0; in pcibios_allocate_bus_resources()
1264 res->end = -1; in pcibios_allocate_bus_resources()
1265 res->flags = 0; in pcibios_allocate_bus_resources()
1268 list_for_each_entry(b, &bus->children, node) in pcibios_allocate_bus_resources()
1274 struct resource *pr, *r = &dev->resource[idx]; in alloc_resource()
1280 if (!pr || (pr->flags & IORESOURCE_UNSET) || in alloc_resource()
1287 r->flags |= IORESOURCE_UNSET; in alloc_resource()
1288 r->end -= r->start; in alloc_resource()
1289 r->start = 0; in alloc_resource()
1303 r = &dev->resource[idx]; in pcibios_allocate_resources()
1304 if (r->parent) /* Already allocated */ in pcibios_allocate_resources()
1306 if (!r->flags || (r->flags & IORESOURCE_UNSET)) in pcibios_allocate_resources()
1313 if (r->flags & IORESOURCE_IO) in pcibios_allocate_resources()
1322 r = &dev->resource[PCI_ROM_RESOURCE]; in pcibios_allocate_resources()
1323 if (r->flags) { in pcibios_allocate_resources()
1328 pci_read_config_dword(dev, dev->rom_base_reg, ®); in pcibios_allocate_resources()
1332 r->flags &= ~IORESOURCE_ROM_ENABLE; in pcibios_allocate_resources()
1333 pci_write_config_dword(dev, dev->rom_base_reg, in pcibios_allocate_resources()
1350 if (!(hose->io_resource.flags & IORESOURCE_IO)) in pcibios_reserve_legacy_regions()
1352 offset = (unsigned long)hose->io_base_virt - _IO_BASE; in pcibios_reserve_legacy_regions()
1355 res->name = "Legacy IO"; in pcibios_reserve_legacy_regions()
1356 res->flags = IORESOURCE_IO; in pcibios_reserve_legacy_regions()
1357 res->start = offset; in pcibios_reserve_legacy_regions()
1358 res->end = (offset + 0xfff) & 0xfffffffful; in pcibios_reserve_legacy_regions()
1360 if (request_resource(&hose->io_resource, res)) { in pcibios_reserve_legacy_regions()
1363 pci_domain_nr(bus), bus->number, res); in pcibios_reserve_legacy_regions()
1370 pres = &hose->mem_resources[i]; in pcibios_reserve_legacy_regions()
1371 offset = hose->mem_offset[i]; in pcibios_reserve_legacy_regions()
1372 if (!(pres->flags & IORESOURCE_MEM)) in pcibios_reserve_legacy_regions()
1375 if ((pres->start - offset) <= 0xa0000 && in pcibios_reserve_legacy_regions()
1376 (pres->end - offset) >= 0xbffff) in pcibios_reserve_legacy_regions()
1383 res->name = "Legacy VGA memory"; in pcibios_reserve_legacy_regions()
1384 res->flags = IORESOURCE_MEM; in pcibios_reserve_legacy_regions()
1385 res->start = 0xa0000 + offset; in pcibios_reserve_legacy_regions()
1386 res->end = 0xbffff + offset; in pcibios_reserve_legacy_regions()
1391 pci_domain_nr(bus), bus->number, res); in pcibios_reserve_legacy_regions()
1428 * rest of the code later, for now, keep it as-is as our main
1429 * resource allocation function doesn't deal with sub-trees yet.
1436 list_for_each_entry(dev, &bus->devices, bus_list) { in pcibios_claim_one_bus()
1440 struct resource *r = &dev->resource[i]; in pcibios_claim_one_bus()
1442 if (r->parent || !r->start || !r->flags) in pcibios_claim_one_bus()
1455 list_for_each_entry(child_bus, &bus->children, node) in pcibios_claim_one_bus()
1470 pci_domain_nr(bus), bus->number); in pcibios_finish_adding_to_bus()
1476 if (bus->self) in pcibios_finish_adding_to_bus()
1477 pci_assign_unassigned_bridge_resources(bus->self); in pcibios_finish_adding_to_bus()
1489 struct pci_controller *phb = pci_bus_to_host(dev->bus); in pcibios_enable_device()
1491 if (phb->controller_ops.enable_device_hook) in pcibios_enable_device()
1492 if (!phb->controller_ops.enable_device_hook(dev)) in pcibios_enable_device()
1493 return -EINVAL; in pcibios_enable_device()
1500 struct pci_controller *phb = pci_bus_to_host(dev->bus); in pcibios_disable_device()
1502 if (phb->controller_ops.disable_device) in pcibios_disable_device()
1503 phb->controller_ops.disable_device(dev); in pcibios_disable_device()
1508 return (unsigned long) hose->io_base_virt - _IO_BASE; in pcibios_io_space_offset()
1519 res = &hose->io_resource; in pcibios_setup_phb_resources()
1521 if (!res->flags) { in pcibios_setup_phb_resources()
1524 hose->dn, hose->global_number); in pcibios_setup_phb_resources()
1535 res = &hose->mem_resources[i]; in pcibios_setup_phb_resources()
1536 if (!res->flags) in pcibios_setup_phb_resources()
1539 offset = hose->mem_offset[i]; in pcibios_setup_phb_resources()
1592 bus.ops = hose? hose->ops: &null_pci_ops; in fake_pci_bus()
1619 struct pci_controller *hose = bus->sysdata; in pcibios_get_phb_of_node()
1621 return of_node_get(hose->dn); in pcibios_get_phb_of_node()
1625 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1632 struct device_node *node = hose->dn; in pcibios_scan_phb()
1643 hose->busn.start = hose->first_busno; in pcibios_scan_phb()
1644 hose->busn.end = hose->last_busno; in pcibios_scan_phb()
1645 hose->busn.flags = IORESOURCE_BUS; in pcibios_scan_phb()
1646 pci_add_resource(&resources, &hose->busn); in pcibios_scan_phb()
1649 bus = pci_create_root_bus(hose->parent, hose->first_busno, in pcibios_scan_phb()
1650 hose->ops, hose, &resources); in pcibios_scan_phb()
1653 hose->global_number); in pcibios_scan_phb()
1657 hose->bus = bus; in pcibios_scan_phb()
1661 if (node && hose->controller_ops.probe_mode) in pcibios_scan_phb()
1662 mode = hose->controller_ops.probe_mode(bus); in pcibios_scan_phb()
1669 hose->last_busno = pci_scan_child_bus(bus); in pcibios_scan_phb()
1670 pci_bus_update_busn_res_end(bus, hose->last_busno); in pcibios_scan_phb()
1682 list_for_each_entry(child, &bus->children, node) in pcibios_scan_phb()
1690 int i, class = dev->class >> 8; in fixup_hide_host_resource_fsl()
1692 int prog_if = dev->class & 0xf; in fixup_hide_host_resource_fsl()
1696 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) && in fixup_hide_host_resource_fsl()
1698 (dev->bus->parent == NULL)) { in fixup_hide_host_resource_fsl()
1700 dev->resource[i].start = 0; in fixup_hide_host_resource_fsl()
1701 dev->resource[i].end = 0; in fixup_hide_host_resource_fsl()
1702 dev->resource[i].flags = 0; in fixup_hide_host_resource_fsl()