Lines Matching refs:li
63 li r24,0 /* CPU number */
111 li r0,0
156 li r4, 0 /* higer 32bit */
205 li r3,0
221 li r0,0
355 li r13,_PAGE_PRESENT|_PAGE_ACCESSED
386 li r13,0
452 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
481 li r13,0
523 li r11,PPC44x_TLB_VALID | PPC44x_TLBE_SIZE
529 li r10,0xf85 /* Mask to apply from PTE */
571 li r12,0 /* MMUCR = 0 */
594 li r13,_PAGE_PRESENT|_PAGE_ACCESSED
603 li r12,PPC47x_TLB0_VALID | PPC47x_TLBE_SIZE
605 li r12,0
668 li r12,0 /* MMUCR = 0 */
678 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
686 li r12,PPC47x_TLB0_VALID | PPC47x_TLBE_SIZE
688 li r12,0
744 li r10,0xf85 /* Mask to apply from PTE */
786 li r3,MachineCheckA@l
859 li r4,0 /* Start at TLB entry 0 */
860 li r3,0 /* Set PAGEID inval value */
893 li r4, 0 /* Load the kernel physical address */
897 li r0,0
902 li r5,0
916 li r5,0
919 li r0,63 /* TLB slot 63 */
937 li r6,0
954 li r5,(PPC44x_TLB_SW|PPC44x_TLB_SR|PPC44x_TLB_I|PPC44x_TLB_G)
955 li r0,62 /* TLB slot 0 */
1006 li r0,0
1019 li r0,0
1060 li r5,0
1105 li r0,0
1116 li r5,0
1168 li r5,(PPC47x_TLB2_S_RW | PPC47x_TLB2_IMG)