Lines Matching refs:r10
108 stw r10,crit_r10@l(0) /* save two registers to work with */
110 mfspr r10,SPRN_SRR0
112 stw r10,crit_srr0@l(0)
114 mfspr r10,SPRN_DEAR
116 stw r10,crit_dear@l(0)
118 mfcr r10 /* save CR in r10 for now */
143 stw r10,_CCR(r11) /* save various registers */
146 mflr r10
147 stw r10,_LINK(r11)
149 lwz r10,crit_r10@l(r9)
151 stw r10,GPR10(r11)
274 mtspr SPRN_SPRG_SCRATCH5, r10 /* Save some working registers */
281 mfspr r10, SPRN_DEAR /* Get faulting address */
287 cmplw r10, r11
302 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
307 rlwimi r11, r10, 22, 20, 29 /* Compute PTE address */
321 rlwimi r10, r9, 0, 20, 31
333 rlwimi r10, r9, 0, 20, 31
346 mfspr r10, SPRN_SPRG_SCRATCH5
354 mtspr SPRN_SPRG_SCRATCH5, r10 /* Save some working registers */
361 mfspr r10, SPRN_SRR0 /* Get faulting address */
367 cmplw r10, r11
382 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
387 rlwimi r11, r10, 22, 20, 29 /* Compute PTE address */
401 rlwimi r10, r9, 0, 20, 31
413 rlwimi r10, r9, 0, 20, 31
426 mfspr r10, SPRN_SPRG_SCRATCH5
468 mfspr r10,SPRN_DBSR /* check single-step/branch taken */
469 andis. r10,r10,DBSR_IC@h
472 andi. r10,r9,MSR_IR|MSR_PR /* check supervisor + MMU off */
475 mfspr r10,SPRN_SRR2 /* Faulting instruction address */
476 cmplwi r10,0x2100
481 lis r10,DBSR_IC@h /* clear the IC event */
482 mtspr SPRN_DBSR,r10
484 lwz r10,_CCR(r11)
487 mtcrf 0x80,r10
492 lwz r10,crit_r10@l(0)
566 tlbwe r10, r9, TLB_TAG /* Load TLB HI */
575 mfspr r10, SPRN_SPRG_SCRATCH5