Lines Matching full:exception
8 * Low-level exception handers, MMU support, and rewrite.
80 * critical exception prolog.
100 * Exception prolog for critical exceptions. This is a little different
101 * from the normal exception prolog above since a critical exception
102 * can potentially occur at any point during normal exception processing.
156 stw r9,_ESR(r11) /* exception was taken */
169 * now phys stack/exception frame pointer
178 * Exception vectors.
188 * 0x0100 - Critical Interrupt Exception
193 * 0x0200 - Machine Check Exception
198 * 0x0300 - Data Storage Exception
211 * 0x0400 - Instruction Storage Exception
223 /* 0x0500 - External Interrupt Exception */
224 EXCEPTION(0x0500, HardwareInterrupt, do_IRQ)
226 /* 0x0600 - Alignment Exception */
234 /* 0x0700 - Program Exception */
242 EXCEPTION(0x0800, Trap_08, unknown_exception)
243 EXCEPTION(0x0900, Trap_09, unknown_exception)
244 EXCEPTION(0x0A00, Trap_0A, unknown_exception)
245 EXCEPTION(0x0B00, Trap_0B, unknown_exception)
247 /* 0x0C00 - System Call Exception */
250 /* Trap_0D is commented out to get more space for system call exception */
252 /* EXCEPTION(0x0D00, Trap_0D, unknown_exception) */
253 EXCEPTION(0x0E00, Trap_0E, unknown_exception)
254 EXCEPTION(0x0F00, Trap_0F, unknown_exception)
256 /* 0x1000 - Programmable Interval Timer (PIT) Exception */
260 /* 0x1010 - Fixed Interval Timer (FIT) Exception */
264 /* 0x1020 - Watchdog Timer (WDT) Exception */
268 /* 0x1100 - Data TLB Miss Exception
338 /* The bailout. Restore registers to pre-exception conditions
349 /* 0x1200 - Instruction TLB Miss Exception
418 /* The bailout. Restore registers to pre-exception conditions
429 EXCEPTION(0x1300, Trap_13, unknown_exception)
430 EXCEPTION(0x1400, Trap_14, unknown_exception)
431 EXCEPTION(0x1500, Trap_15, unknown_exception)
432 EXCEPTION(0x1600, Trap_16, unknown_exception)
433 EXCEPTION(0x1700, Trap_17, unknown_exception)
434 EXCEPTION(0x1800, Trap_18, unknown_exception)
435 EXCEPTION(0x1900, Trap_19, unknown_exception)
436 EXCEPTION(0x1A00, Trap_1A, unknown_exception)
437 EXCEPTION(0x1B00, Trap_1B, unknown_exception)
438 EXCEPTION(0x1C00, Trap_1C, unknown_exception)
439 EXCEPTION(0x1D00, Trap_1D, unknown_exception)
440 EXCEPTION(0x1E00, Trap_1E, unknown_exception)
441 EXCEPTION(0x1F00, Trap_1F, unknown_exception)
443 /* Check for a single step debug exception while in an exception
446 * an exception (eg ITLB/DTLB miss) and thus the first instruction of
447 * the exception handler generates a single step debug exception.
449 * If we get a debug trap on the first instruction of an exception handler,
451 * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR).
452 * The exception handler was handling a non-critical interrupt, so it will
456 /* 0x2000 - Debug Exception */
461 * If this is a single step or branch-taken exception in an
462 * exception entry sequence, it was probably meant to apply to
463 * the code where the exception occurred (since exception entry
465 * of turning off DE on entry to an exception handler by turning
477 bgt+ 2f /* address above exception vectors */
479 /* here it looks like we got an inappropriate debug exception. */
497 /* continue normal handling for a critical exception... */
504 /* Programmable Interval Timer (PIT) Exception. (from 0x1000) */
509 mtspr SPRN_TSR,r0 /* Clear the PIT exception */
514 /* Fixed Interval Timer (FIT) Exception. (from 0x1010) */
522 /* Watchdog Timer (WDT) Exception. (from 0x1020) */
538 * exception space :-). Both the instruction and data TLB
612 * and change to using our exception vectors.
692 /* Establish the exception vector base