Lines Matching +full:protect +full:- +full:exec

1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <asm-generic/pgtable-nopmd.h>
8  * The "classic" 32-bit implementation of the PowerPC MMU uses a hash
13  * active mappings.  We maintain a two-level page table tree, much
15  * management code.  Low-level assembler code in hash_low_32.S
27 #define _PAGE_WRITETHRU	0x040	/* W: cache write-through */
30 #define _PAGE_EXEC	0x200	/* software: exec allowed */
63  * Location of the PFN in the PTE. Most 32-bit platforms use the same
65  * Platform who don't just pre-define the value so we don't override it here.
70  * The mask covered by the RPN must be a ULL on 32-bit platforms with
71  * 64-bit PTEs.
74 #define PTE_RPN_MASK	(~((1ULL << PTE_RPN_SHIFT) - 1))
77 #define PTE_RPN_MASK	(~((1UL << PTE_RPN_SHIFT) - 1))
123  * set breakpoints anywhere, so don't write protect the kernel text
143 #define PGD_INDEX_SIZE	(32 - PGDIR_SHIFT)
155 #define PMD_MASKED_BITS		(PTE_TABLE_SIZE - 1)
162  * The normal case is that PTEs are 32-bits and we have a 1-page
163  * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages.  -- paulus
165  * For any >32-bit physical address platform, we can use the following
168  * level has 2048 entries and the second level has 512 64-bit PTE entries.
169  * -Matt
171 /* PGDIR_SHIFT determines what a top-level page table entry can map */
174 #define PGDIR_MASK	(~(PGDIR_SIZE-1))
210  * any out-of-bounds memory accesses will hopefully be caught.
221  * of RAM.  -- Cort
225 #define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
234 #define MODULES_VADDR	(MODULES_END - SZ_256M)
249  * Bits in a linux-style PTE.  These match the bits in the
250  * (hardware-defined) PowerPC PTE as closely as possible.
282 		flush_hash_pages(mm->context.id, addr, ptephys, 1);  in flush_hash_entry()
288  * valid PTE is updated. This does -not- include set_pte_at()
308 "	lwz	%0, -4(%3)\n"  in pte_update()
313 "	bne-	1b"  in pte_update()
328  * for our hash-based implementation, we fix that up here.
342 	__ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep)
366 	pte_update(vma->vm_mm, address, ptep, 0, set, 0);  in __ptep_set_access_flags()
381  *   -- paulus
426 	 * A read-only access is controlled by _PAGE_USER bit.  in pte_access_permitted()
537 	/* First case is 32-bit Hash MMU in SMP mode with 32-bit PTEs. We use the  in __set_pte_at()
540 	 * per-CPU PTE such as a kmap_atomic, we do a simple update preserving  in __set_pte_at()
541 	 * the hash bits instead (ie, same as the non-SMP case)  in __set_pte_at()
550 	/* Second case is 32-bit with 64-bit PTE.  In this case, we  in __set_pte_at()
553 	 * in the hash code, to pre-invalidate if the PTE was already hashed,  in __set_pte_at()
573 	/* Third case is 32-bit hash table in UP mode, we need to preserve  in __set_pte_at()