Lines Matching +full:pdc +full:- +full:global
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Linux/PA-RISC Project (http://www.parisc-linux.org/)
8 * Copyright (C) 2000 Hewlett-Packard (John Marvin)
9 * Copyright (C) 1999 Hewlett-Packard (Frank Rowand)
12 #include <asm/asm-offsets.h>
15 * - handle in assembly and use shadowed registers only
16 * - save registers to kernel stack and handle in assembly or C */
51 extrd,u \spc,(64 - (SPACEID_SHIFT)),32,\prot
97 * to use a non-shadowed register to carry the value over
102 * be a non-shadowed register so that it survives the rfir.
117 LDREG TI_TASK(%r9), %r1 /* thread_info -> task_struct */
190 * itlb miss interruption handler (parisc 1.1 - 32 bit)
221 * naitlb miss interruption handler (parisc 1.1 - 32 bit)
253 * dtlb miss interruption handler (parisc 1.1 - 32 bit)
284 /* nadtlb miss interruption handler (parisc 1.1 - 32 bit) */
313 * dirty bit trap interruption handler (parisc 1.1 - 32 bit)
369 spc - The space we saw the fault with.
370 tmp - The place to store the current space.
371 fault - Function to call on failure.
388 /* Look up a PTE in a 2-Level scheme (faulting at each
396 extru \va,31-ASM_PMD_SHIFT,ASM_BITS_PER_PMD,\index
399 extrd,u \va,63-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
402 extru \va,31-ASM_PGDIR_SHIFT,32-ASM_PGDIR_SHIFT,\index
404 extru \va,31-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
416 extru \va,31-PAGE_SHIFT,ASM_BITS_PER_PTE,\index
421 /* Look up PTE in a 3-Level scheme. */
425 extrd,u \va,63-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
493 * - 38 to 52-bit Physical Page Number
494 * - 12 to 26-bit page offset
498 #define PAGE_ADD_SHIFT (PAGE_SHIFT-12)
499 #define PAGE_ADD_HUGE_SHIFT (REAL_HPAGE_SHIFT-12)
505 extrd,u \tmp,(63-ASM_PFN_PTE_SHIFT)+(63-58)+PAGE_ADD_SHIFT,\
506 64-PAGE_SHIFT-PAGE_ADD_SHIFT,\pte
509 (63-58)+PAGE_ADD_SHIFT,\pte
512 (63-58)+PAGE_ADD_HUGE_SHIFT,\pte
514 extrd,u \pte,(63-ASM_PFN_PTE_SHIFT)+(63-58)+PAGE_ADD_SHIFT,\
515 64-PAGE_SHIFT-PAGE_ADD_SHIFT,\pte
517 (63-58)+PAGE_ADD_SHIFT,\pte
526 * T <-> _PAGE_REFTRAP
527 * D <-> _PAGE_DIRTY
528 * B <-> _PAGE_DMB (memory break)
532 * See 3-14 of the parisc 2.0 manual
553 * (that means T-class is NOT supported) and the memory controllers
579 SHRREG \pte,(ASM_PFN_PTE_SHIFT-(31-26)),\pte
598 * the from tlb entry (or nothing if only a to entry---for
760 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
779 STREG %r2, -RP_OFFSET(%r30)
800 LDREG -RP_OFFSET(%r30), %r2
823 LDREG TI_TASK(%r16), %r16 /* thread_info -> task_struct */
869 bb,<,n %r19,31-TIF_NEED_RESCHED,intr_do_resched /* forward */
894 ldo -16(%r30),%r29 /* Reference param save area */
953 ldo -16(%r30),%r29 /* Reference param save area */
975 /* current_thread_info()->preempt_count */
983 bb,<,n %r20, 31 - PSW_SM_I, intr_restore
1027 ldo -16(%r30),%r29 /* Reference param save area */
1076 /* Revisit when we have 64-bit code above 4Gb */
1107 ldo -16(%r30),%r29 /* Reference param save area */
1328 * Non access misses can be caused by fdc,fic,pdc,lpa,probe and
1337 * emulate fdc,fic,pdc,probew,prober instructions whose base
1345 Checks for fdc,fdce,pdc,"fic,4f",prober,probeir,probew, probeiw */
1347 /* Checks for fdc,fdce,pdc,"fic,4f" only */
1354 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1358 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1380 WARNING: USE ONLY NON-SHADOW REGISTERS WITH PROBE INSN!
1381 THE SLOW-PATH EMULATION HAS NOT BEEN WRITTEN YET.
1390 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1661 %r3 - %r18 preserved by C code (saved by signal code)
1662 %r19 - %r20 saved in PT_REGS by gateway page
1663 %r21 - %r22 non-standard syscall args
1665 %r23 - %r26 arg3-arg0, saved in PT_REGS by gateway page
1666 %r27 - %r30 saved in PT_REGS by gateway page
1672 %fr0 - %fr3 status/exception, not preserved
1673 %fr4 - %fr7 arguments
1674 %fr8 - %fr11 not preserved by C code
1675 %fr12 - %fr21 preserved by C code
1676 %fr22 - %fr31 not preserved by C code
1719 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
1739 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
1750 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r26
1753 STREG %r2, -RP_OFFSET(%r30)
1757 ldo -16(%r30),%r29 /* Reference param save area */
1763 ldo -FRAME_SIZE(%r30), %r30
1764 LDREG -RP_OFFSET(%r30), %r2
1767 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1800 LDREG TI_FLAGS-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r19 /* long */
1801 bb,<,n %r19, 31-TIF_NEED_RESCHED, syscall_do_resched /* forward */
1805 LDREG TI_FLAGS-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r19
1811 /* Save callee-save registers (for sigcontext).
1816 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1821 ldo -16(%r30),%r29 /* Reference param save area */
1827 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1834 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1896 ldo -1(%r0),%r2 /* Set recovery cntr to -1 */
1900 depi -1,13,1,%r20 /* C, Q, D, and I bits */
1904 * numbers in asm-offsets.c */
1908 depi -1,27,1,%r20 /* R bit */
1912 depi -1,7,1,%r20 /* T bit */
1931 * We could make this more efficient by not saving r3-r18, but
1974 ldo -16(%r30),%r29 /* Reference param save area */
2008 .dword 0 /* code in head.S puts value of global gp here */
2021 .global ftrace_caller
2023 STREG %r3, -FTRACE_FRAME_SIZE+1*REG_SZ(%sp)
2024 ldo -FTRACE_FRAME_SIZE(%sp), %r3
2025 STREG %rp, -RP_OFFSET(%r3)
2042 ldo -16(%sp),%r29
2046 ldo -8(%r25), %r25
2051 LDREG -RP_OFFSET(%r3), %rp
2068 LDREGM -FTRACE_FRAME_SIZE(%sp), %r1
2070 ldo -4(%r1), %r1
2079 .global ftrace_regs_caller
2081 ldo -FTRACE_FRAME_SIZE(%sp), %r1
2082 STREG %rp, -RP_OFFSET(%r1)
2121 LDREG -FTRACE_FRAME_SIZE-PT_SZ_ALGN(%sp), %r25
2122 ldo -8(%r25), %r25
2123 ldo -FTRACE_FRAME_SIZE(%r1), %arg2
2127 ldo -PT_SZ_ALGN(%sp), %r1
2163 ldo -PT_SZ_ALGN(%sp), %sp
2164 LDREGM -FTRACE_FRAME_SIZE(%sp), %r1
2166 ldo -4(%r1), %r1
2180 STREG %r0,-RP_OFFSET(%sp) /* store 0 as %rp */
2195 ldo -16(%sp),%ret1 /* Reference param save area */
2214 LDREGM -FRAME_SIZE(%sp),%r3
2237 STREG %rp, -FRAME_SIZE-RP_OFFSET(%sp)
2241 STREG %r1, -FRAME_SIZE-REG_SZ(%sp)
2242 LDREG -FRAME_SIZE-RP_OFFSET(%sp), %rp
2244 LDREG -FRAME_SIZE-REG_SZ(%sp), %sp
2247 STREG %r1, -FRAME_SIZE-REG_SZ(%sp)
2248 STREG %rp, -FRAME_SIZE-RP_OFFSET(%sp)
2256 LDREG -FRAME_SIZE-RP_OFFSET(%sp), %rp
2258 LDREG -FRAME_SIZE-REG_SZ(%sp), %sp
2269 * registers we put a -1 into r1 to indicate that the register
2271 * a -1 in it, but that is OK, it just means that we will have
2278 bv %r0(%r25) /* r1 - shadowed */
2279 ldi -1,%r1
2292 bv %r0(%r25) /* r8 - shadowed */
2293 ldi -1,%r1
2294 bv %r0(%r25) /* r9 - shadowed */
2295 ldi -1,%r1
2308 bv %r0(%r25) /* r16 - shadowed */
2309 ldi -1,%r1
2310 bv %r0(%r25) /* r17 - shadowed */
2311 ldi -1,%r1
2324 bv %r0(%r25) /* r24 - shadowed */
2325 ldi -1,%r1
2326 bv %r0(%r25) /* r25 - shadowed */
2327 ldi -1,%r1