Lines Matching +full:left +full:- +full:shifted
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
26 #include <asm/asm-offsets.h>
30 l.movhi rd,hi(-KERNELBASE) ;\
172 /* Load r10 from current_thread_info_set - clobbers r1 and r30 */
195 * PRMS: handler - a function to jump to. it has to save the
197 * appropriate arch-independant exception handler
205 * r1 - ksp pointing to the new (exception) frame
206 * r4 - EEAR exception EA
207 * r10 - current pointing to current_thread_info struct
208 * r12 - syscall 0, since we didn't come from syscall
209 * r30 - handler address of the handler we'll jump to
238 l.addi r1,r1,-(INT_FRAME_SIZE) ;\
261 /* ----- turn on MMU ----- */ ;\
322 l.addi r1,r1,-(INT_FRAME_SIZE) ;\
340 /* --> */ ;\
346 /* ----- play a MMU trick ----- */ ;\
356 /* ---[ 0x100: RESET exception ]----------------------------------------- */
366 /* ---[ 0x200: BUS exception ]------------------------------------------- */
371 /* ---[ 0x300: Data Page Fault exception ]------------------------------- */
380 /* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
389 /* ---[ 0x500: Timer exception ]----------------------------------------- */
393 /* ---[ 0x600: Alignment exception ]-------------------------------------- */
397 /* ---[ 0x700: Illegal insn exception ]---------------------------------- */
401 /* ---[ 0x800: External interrupt exception ]---------------------------- */
405 /* ---[ 0x900: DTLB miss exception ]------------------------------------- */
410 /* ---[ 0xa00: ITLB miss exception ]------------------------------------- */
415 /* ---[ 0xb00: Range exception ]----------------------------------------- */
419 /* ---[ 0xc00: Syscall exception ]--------------------------------------- */
423 /* ---[ 0xd00: Trap exception ]------------------------------------------ */
427 /* ---[ 0xe00: Trap exception ]------------------------------------------ */
432 /* ---[ 0xf00: Reserved exception ]-------------------------------------- */
436 /* ---[ 0x1000: Reserved exception ]------------------------------------- */
440 /* ---[ 0x1100: Reserved exception ]------------------------------------- */
444 /* ---[ 0x1200: Reserved exception ]------------------------------------- */
448 /* ---[ 0x1300: Reserved exception ]------------------------------------- */
452 /* ---[ 0x1400: Reserved exception ]------------------------------------- */
456 /* ---[ 0x1500: Reserved exception ]------------------------------------- */
460 /* ---[ 0x1600: Reserved exception ]------------------------------------- */
464 /* ---[ 0x1700: Reserved exception ]------------------------------------- */
468 /* ---[ 0x1800: Reserved exception ]------------------------------------- */
472 /* ---[ 0x1900: Reserved exception ]------------------------------------- */
476 /* ---[ 0x1a00: Reserved exception ]------------------------------------- */
480 /* ---[ 0x1b00: Reserved exception ]------------------------------------- */
484 /* ---[ 0x1c00: Reserved exception ]------------------------------------- */
488 /* ---[ 0x1d00: Reserved exception ]------------------------------------- */
492 /* ---[ 0x1e00: Reserved exception ]------------------------------------- */
496 /* ---[ 0x1f00: Reserved exception ]------------------------------------- */
575 * .bss contains uninitialized data - clear it up
707 l.addi r7,r7,-1
743 /* Wakeup - Restore exception handler */
748 * Check if we actually got the release signal, if not go-back to
823 l.addi r5,r0,-1
889 l.addi r5,r0,-1
943 /* ---[ boot dtlb miss handler ]----------------------------------------- */
947 /* mask for DTLB_MR register: - (0) sets V (valid) bit,
948 * - (31-12) sets bits belonging to VPN (31-12)
952 /* mask for DTLB_TR register: - (2) sets CI (cache inhibit) bit,
953 * - (4) sets A (access) bit,
954 * - (5) sets D (dirty) bit,
955 * - (8) sets SRE (superuser read) bit
956 * - (9) sets SWE (superuser write) bit
957 * - (31-12) sets bits belonging to VPN (31-12)
972 l.sfeqi r6,0 // r6 == 0x1 --> SM
992 …l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VPN…
999 l.addi r6, r5, -1 // r6 = nsets mask
1000 l.and r2, r3, r6 // r2 <- r3 % NSETS_MASK
1002 l.or r6,r6,r4 // r6 <- r4
1003 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
1004 l.movhi r5,hi(DTLB_MR_MASK) // r5 <- ffff:0000.x000
1005 l.ori r5,r5,lo(DTLB_MR_MASK) // r5 <- ffff:1111.x001 - apply DTLB_MR_MASK
1006 l.and r5,r5,r6 // r5 <- VPN :VPN .x001 - we have DTLBMR entry
1013 l.and r3,r4,r4 // delay slot :: 24 <- r4 (if flag==1)
1015 tophys(r3,r4) // r3 <- PA
1017 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
1018 l.movhi r5,hi(DTLB_TR_MASK) // r5 <- ffff:0000.x000
1019 l.ori r5,r5,lo(DTLB_TR_MASK) // r5 <- ffff:1111.x330 - apply DTLB_MR_MASK
1020 l.and r5,r5,r3 // r5 <- PPN :PPN .x330 - we have DTLBTR entry
1029 l.rfe // SR <- ESR, PC <- EPC
1037 /* ---[ boot itlb miss handler ]----------------------------------------- */
1041 /* mask for ITLB_MR register: - sets V (valid) bit,
1042 * - sets bits belonging to VPN (15-12)
1046 /* mask for ITLB_TR register: - sets A (access) bit,
1047 * - sets SXE (superuser execute) bit
1048 * - sets bits belonging to VPN (15-12)
1068 l.sfeqi r6,0 // r6 == 0x1 --> SM
1079 …l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VP…
1086 l.addi r6, r5, -1 // r6 = nsets mask
1087 l.and r2, r3, r6 // r2 <- r3 % NSETS_MASK
1089 l.or r6,r6,r4 // r6 <- r4
1090 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
1091 l.movhi r5,hi(ITLB_MR_MASK) // r5 <- ffff:0000.x000
1092 l.ori r5,r5,lo(ITLB_MR_MASK) // r5 <- ffff:1111.x001 - apply ITLB_MR_MASK
1093 l.and r5,r5,r6 // r5 <- VPN :VPN .x001 - we have ITLBMR entry
1106 l.and r3,r4,r4 // delay slot :: 24 <- r4 (if flag==1)
1108 tophys(r3,r4) // r3 <- PA
1110 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
1111 l.movhi r5,hi(ITLB_TR_MASK) // r5 <- ffff:0000.x000
1112 l.ori r5,r5,lo(ITLB_TR_MASK) // r5 <- ffff:1111.x050 - apply ITLB_MR_MASK
1113 l.and r5,r5,r3 // r5 <- PPN :PPN .x050 - we have ITLBTR entry
1122 l.rfe // SR <- ESR, PC <- EPC
1158 l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
1178 l.andi r3,r2,0x7ff // (1UL << PAGE_SHIFT - 2) - 1
1199 l.addi r2, r3, -1 // r2 = nsets mask
1202 l.and r2, r3, r2 // calc offset: & (NUM_TLB_ENTRIES-1)
1238 l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
1259 l.andi r3,r2,0x7ff // (1UL << PAGE_SHIFT - 2) - 1
1284 l.addi r2, r3, -1 // r2 = nsets mask
1287 l.and r2, r3, r2 // calc offset: & (NUM_TLB_ENTRIES-1)
1351 // EPC = EEA - 0x4
1354 l.lwz r4,-0x4(r6) // load op @ EEA - 0x4 (f8 address)
1387 * where 0xaaaabbbb is EEA + 0x4 shifted right 2
1408 l.slli r6,r4,6 // original offset shifted left 6 - 2
1409 // l.srli r6,r6,6 // original offset shifted right 2
1411 l.slli r4,r2,4 // old jump position: EEA shifted left 4
1412 // l.srli r4,r4,6 // old jump position: shifted right 2
1415 l.slli r5,r5,4 // new jump position: shifted left 4
1418 // new_off = old_off + (old_jump - new_jump)
1420 l.sub r5,r4,r5 // old_jump - new_jump
1421 l.add r5,r6,r5 // orig_off + (old_jump - new_jump)
1422 l.srli r5,r5,6 // new offset shifted right 2
1431 /* ----------------------------- */
1438 * where 0xaaaabbbb is EEA + 0x4 shifted right 2
1457 l.ori r5,r5,0x4400 // opcode changed from l.jalr -> l.jr
1466 /* ----------------------------- */
1470 l.slli r6,r4,6 // original offset shifted left 6 - 2
1471 // l.srli r6,r6,6 // original offset shifted right 2
1473 l.slli r4,r2,4 // old jump position: EEA shifted left 4
1474 // l.srli r4,r4,6 // old jump position: shifted right 2
1477 l.slli r5,r5,4 // new jump position: shifted left 4
1480 // new_off = old_off + (old_jump - new_jump)
1483 l.sub r6,r6,r5 // (orig_off + old_jump) - new_jump
1484 l.srli r6,r6,6 // new offset shifted right 2
1496 l.addi r4,r4,(0x8 - 0x8) // jump target = r2 + 0x8 (compensate for 0x8)
1498 l.sub r4,r4,r5 // jump offset = target - new_position + 0x8
1537 * PRMS: r3 - address of the first character of null
1596 l.addi r8,r8,-0x4
1644 l.addi r8,r8,-0x4