Lines Matching +full:0 +full:x1b00
34 l.movhi gpr,0x0
41 #define UART_BASE_ADD 0x90000000
73 #define EMERGENCY_PRINT_STORE_GPR4 l.sw 0x20(r0),r4
74 #define EMERGENCY_PRINT_LOAD_GPR4 l.lwz r4,0x20(r0)
76 #define EMERGENCY_PRINT_STORE_GPR5 l.sw 0x24(r0),r5
77 #define EMERGENCY_PRINT_LOAD_GPR5 l.lwz r5,0x24(r0)
79 #define EMERGENCY_PRINT_STORE_GPR6 l.sw 0x28(r0),r6
80 #define EMERGENCY_PRINT_LOAD_GPR6 l.lwz r6,0x28(r0)
82 #define EMERGENCY_PRINT_STORE_GPR7 l.sw 0x2c(r0),r7
83 #define EMERGENCY_PRINT_LOAD_GPR7 l.lwz r7,0x2c(r0)
85 #define EMERGENCY_PRINT_STORE_GPR8 l.sw 0x30(r0),r8
86 #define EMERGENCY_PRINT_LOAD_GPR8 l.lwz r8,0x30(r0)
88 #define EMERGENCY_PRINT_STORE_GPR9 l.sw 0x34(r0),r9
89 #define EMERGENCY_PRINT_LOAD_GPR9 l.lwz r9,0x34(r0)
113 #define EXCEPTION_STORE_GPR2 l.sw 0x64(r0),r2
114 #define EXCEPTION_LOAD_GPR2 l.lwz r2,0x64(r0)
116 #define EXCEPTION_STORE_GPR3 l.sw 0x68(r0),r3
117 #define EXCEPTION_LOAD_GPR3 l.lwz r3,0x68(r0)
119 #define EXCEPTION_STORE_GPR4 l.sw 0x6c(r0),r4
120 #define EXCEPTION_LOAD_GPR4 l.lwz r4,0x6c(r0)
122 #define EXCEPTION_STORE_GPR5 l.sw 0x70(r0),r5
123 #define EXCEPTION_LOAD_GPR5 l.lwz r5,0x70(r0)
125 #define EXCEPTION_STORE_GPR6 l.sw 0x74(r0),r6
126 #define EXCEPTION_LOAD_GPR6 l.lwz r6,0x74(r0)
145 #define EXCEPTION_T_STORE_GPR30 l.sw 0x78(r0),r30
146 #define EXCEPTION_T_LOAD_GPR30(reg) l.lwz reg,0x78(r0)
148 #define EXCEPTION_T_STORE_GPR10 l.sw 0x7c(r0),r10
149 #define EXCEPTION_T_LOAD_GPR10(reg) l.lwz reg,0x7c(r0)
151 #define EXCEPTION_T_STORE_SP l.sw 0x80(r0),r1
152 #define EXCEPTION_T_LOAD_SP(reg) l.lwz reg,0x80(r0)
164 l.lwz reg,0(t1)
169 l.lwz reg,0(t1)
181 l.lwz r10,0(r30)
187 l.lwz r10,0(r30)
208 * r12 - syscall 0, since we didn't come from syscall
225 l.sfeqi r30,0 ;\
278 * l.ori r3,r0,0x1 ;\
280 * l.movhi r3,hi(0xf0000100) ;\
281 * l.ori r3,r3,lo(0xf0000100) ;\
298 l.addi r1,r3,0x0 ;\
299 l.addi r10,r9,0x0 ;\
305 l.andi r3,r3,0x1f00 ;\
314 l.addi r3,r1,0x0 ;\
315 l.addi r9,r10,0x0 ;\
356 /* ---[ 0x100: RESET exception ]----------------------------------------- */
357 .org 0x100
366 /* ---[ 0x200: BUS exception ]------------------------------------------- */
367 .org 0x200
371 /* ---[ 0x300: Data Page Fault exception ]------------------------------- */
372 .org 0x300
376 // DEBUG_TLB_PROBE(0x300)
377 // EXCEPTION_DEBUG_VALUE_ER_ENABLED(0x300)
380 /* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
381 .org 0x400
385 // DEBUG_TLB_PROBE(0x400)
386 // EXCEPTION_DEBUG_VALUE_ER_ENABLED(0x400)
389 /* ---[ 0x500: Timer exception ]----------------------------------------- */
390 .org 0x500
393 /* ---[ 0x600: Alignment exception ]-------------------------------------- */
394 .org 0x600
397 /* ---[ 0x700: Illegal insn exception ]---------------------------------- */
398 .org 0x700
401 /* ---[ 0x800: External interrupt exception ]---------------------------- */
402 .org 0x800
405 /* ---[ 0x900: DTLB miss exception ]------------------------------------- */
406 .org 0x900
410 /* ---[ 0xa00: ITLB miss exception ]------------------------------------- */
411 .org 0xa00
415 /* ---[ 0xb00: Range exception ]----------------------------------------- */
416 .org 0xb00
419 /* ---[ 0xc00: Syscall exception ]--------------------------------------- */
420 .org 0xc00
423 /* ---[ 0xd00: Trap exception ]------------------------------------------ */
424 .org 0xd00
427 /* ---[ 0xe00: Trap exception ]------------------------------------------ */
428 .org 0xe00
432 /* ---[ 0xf00: Reserved exception ]-------------------------------------- */
433 .org 0xf00
436 /* ---[ 0x1000: Reserved exception ]------------------------------------- */
437 .org 0x1000
440 /* ---[ 0x1100: Reserved exception ]------------------------------------- */
441 .org 0x1100
444 /* ---[ 0x1200: Reserved exception ]------------------------------------- */
445 .org 0x1200
448 /* ---[ 0x1300: Reserved exception ]------------------------------------- */
449 .org 0x1300
452 /* ---[ 0x1400: Reserved exception ]------------------------------------- */
453 .org 0x1400
456 /* ---[ 0x1500: Reserved exception ]------------------------------------- */
457 .org 0x1500
460 /* ---[ 0x1600: Reserved exception ]------------------------------------- */
461 .org 0x1600
464 /* ---[ 0x1700: Reserved exception ]------------------------------------- */
465 .org 0x1700
468 /* ---[ 0x1800: Reserved exception ]------------------------------------- */
469 .org 0x1800
472 /* ---[ 0x1900: Reserved exception ]------------------------------------- */
473 .org 0x1900
476 /* ---[ 0x1a00: Reserved exception ]------------------------------------- */
477 .org 0x1a00
480 /* ---[ 0x1b00: Reserved exception ]------------------------------------- */
481 .org 0x1b00
484 /* ---[ 0x1c00: Reserved exception ]------------------------------------- */
485 .org 0x1c00
488 /* ---[ 0x1d00: Reserved exception ]------------------------------------- */
489 .org 0x1d00
492 /* ---[ 0x1e00: Reserved exception ]------------------------------------- */
493 .org 0x1e00
496 /* ---[ 0x1f00: Reserved exception ]------------------------------------- */
497 .org 0x1f00
500 .org 0x2000
521 l.ori r3,r0,0x1
570 l.ori r4,r0,0x0
585 l.sw (0)(r28),r0
607 * SR[5] = 0, SR[6] = 0, 6th and 7th bit of SR set to 0
635 l.lwz r3,0(r25) /* load magic from fdt into r3 */
696 LOAD_SYMBOL_2_GPR(r5,SPR_DTLBMR_BASE(0))
697 LOAD_SYMBOL_2_GPR(r6,SPR_ITLBMR_BASE(0))
700 l.mtspr r5,r0,0x0
701 l.mtspr r6,r0,0x0
734 l.ori r25,r25,0xffff
754 l.lwz r3,0(r4)
766 l.lwz r10,0(r30)
811 .align 0x2000
829 If BS=0, 16;
849 l.addi r6,r0,0
895 If BS=0, 16;
915 l.addi r6,r0,0
933 #define DTLB_UP_CONVERT_MASK 0x3fa
934 #define ITLB_UP_CONVERT_MASK 0x3a
940 #define DTLB_SMP_CONVERT_MASK 0x3fb
941 #define ITLB_SMP_CONVERT_MASK 0x3b
947 /* mask for DTLB_MR register: - (0) sets V (valid) bit,
950 #define DTLB_MR_MASK 0xfffff001
959 #define DTLB_TR_MASK 0xfffff332
963 #define VPN_MASK 0xfffff000
964 #define PPN_MASK 0xfffff000
969 #if 0
972 l.sfeqi r6,0 // r6 == 0x1 --> SM
992 …l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VPN…
997 l.ori r5, r0, 0x1
1003 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
1007 l.mtspr r2,r5,SPR_DTLBMR_BASE(0) // set DTLBMR
1009 /* set up DTLB with no translation for EA <= 0xbfffffff */
1010 LOAD_SYMBOL_2_GPR(r6,0xbfffffff)
1011 l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xbfffffff >= EA)
1017 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
1021 l.mtspr r2,r5,SPR_DTLBTR_BASE(0) // set DTLBTR
1044 #define ITLB_MR_MASK 0xfffff001
1050 #define ITLB_TR_MASK 0xfffff050
1053 #define VPN_MASK 0xffffe000
1054 #define PPN_MASK 0xffffe000
1065 #if 0
1068 l.sfeqi r6,0 // r6 == 0x1 --> SM
1079 …l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VP…
1084 l.ori r5, r0, 0x1
1090 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
1094 l.mtspr r2,r5,SPR_ITLBMR_BASE(0) // set ITLBMR
1097 * set up ITLB with no translation for EA <= 0x0fffffff
1103 LOAD_SYMBOL_2_GPR(r6,0x0fffffff)
1104 l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xb0ffffff >= EA)
1110 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
1114 l.mtspr r2,r5,SPR_ITLBTR_BASE(0) // set ITLBTR
1158 l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
1159 l.slli r4,r4,0x2 // to get address << 2
1166 l.lwz r3,0x0(r4) // get *pmd value
1169 l.addi r3,r0,0xffffe000 // PAGE_MASK
1175 l.lwz r4,0x0(r4) // get **pmd value
1177 l.srli r2,r2,0xd // >> PAGE_SHIFT, r2 == EEAR
1178 l.andi r3,r2,0x7ff // (1UL << PAGE_SHIFT - 2) - 1
1179 l.slli r3,r3,0x2 // to get address << 2
1181 l.lwz r3,0x0(r3) // this is pte at last
1185 l.andi r4,r3,0x1
1188 l.addi r4,r0,0xffffe3fa // PAGE_MASK | DTLB_UP_CONVERT_MASK
1197 l.ori r3, r0, 0x1
1201 l.srli r3, r3, 0xd // >> PAGE_SHIFT
1204 l.mtspr r2,r4,SPR_DTLBTR_BASE(0)
1208 l.slli r3, r3, 0xd /* << PAGE_SHIFT => EA & PAGE_MASK */
1209 l.ori r4,r3,0x1 // set hardware valid bit: DTBL_MR entry
1210 l.mtspr r2,r4,SPR_DTLBMR_BASE(0)
1238 l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
1239 l.slli r4,r4,0x2 // to get address << 2
1246 l.lwz r3,0x0(r4) // get *pmd value
1249 l.addi r3,r0,0xffffe000 // PAGE_MASK
1256 l.lwz r4,0x0(r4) // get **pmd value
1258 l.srli r2,r2,0xd // >> PAGE_SHIFT, r2 == EEAR
1259 l.andi r3,r2,0x7ff // (1UL << PAGE_SHIFT - 2) - 1
1260 l.slli r3,r3,0x2 // to get address << 2
1262 l.lwz r3,0x0(r3) // this is pte at last
1267 l.andi r4,r3,0x1
1270 l.addi r4,r0,0xffffe03a // PAGE_MASK | ITLB_UP_CONVERT_MASK
1275 l.andi r3,r3,0x7c0 // _PAGE_EXEC | _PAGE_SRE | _PAGE_SWE | _PAGE_URE | _PAGE_UWE
1282 l.ori r3, r0, 0x1
1286 l.srli r3, r3, 0xd // >> PAGE_SHIFT
1297 l.ori r4,r4,0xc0 // | (SPR_ITLBTR_UXE | ITLBTR_SXE)
1299 l.mtspr r2,r4,SPR_ITLBTR_BASE(0)
1303 l.slli r3, r3, 0xd /* << PAGE_SHIFT => EA & PAGE_MASK */
1304 l.ori r4,r3,0x1 // set hardware valid bit: ITBL_MR entry
1305 l.mtspr r2,r4,SPR_ITLBMR_BASE(0)
1329 #define TRAMP_SLOT_0 (0x0)
1330 #define TRAMP_SLOT_1 (0x4)
1331 #define TRAMP_SLOT_2 (0x8)
1332 #define TRAMP_SLOT_3 (0xc)
1333 #define TRAMP_SLOT_4 (0x10)
1334 #define TRAMP_SLOT_5 (0x14)
1335 #define TRAMP_FRAME_SIZE (0x18)
1345 LOAD_SYMBOL_2_GPR(r4,0x15000000)
1351 // EPC = EEA - 0x4
1352 l.lwz r4,0x0(r6) // load op @ EEA + 0x0 (fc address)
1354 l.lwz r4,-0x4(r6) // load op @ EEA - 0x4 (f8 address)
1358 l.sfeqi r5,0 // l.j
1359 l.bf 0f
1360 l.sfeqi r5,0x11 // l.jr
1364 l.sfeqi r5,0x12 // l.jalr
1384 /* 19 20 aa aa l.movhi r9,0xaaaa
1385 * a9 29 bb bb l.ori r9,0xbbbb
1387 * where 0xaaaabbbb is EEA + 0x4 shifted right 2
1390 l.addi r6,r2,0x4 // this is 0xaaaabbbb
1392 // l.movhi r9,0xaaaa
1393 l.ori r5,r0,0x1920 // 0x1920 == l.movhi r9
1394 l.sh (TRAMP_SLOT_0+0x0)(r3),r5
1396 l.sh (TRAMP_SLOT_0+0x2)(r3),r5
1398 // l.ori r9,0xbbbb
1399 l.ori r5,r0,0xa929 // 0xa929 == l.ori r9
1400 l.sh (TRAMP_SLOT_1+0x0)(r3),r5
1401 l.andi r5,r6,0xffff
1402 l.sh (TRAMP_SLOT_1+0x2)(r3),r5
1407 0: // l.j
1414 l.addi r5,r3,0xc // new jump position (physical)
1425 // l.j has opcode 0x0...
1435 /* 19 20 aa aa l.movhi r9,0xaaaa
1436 * a9 29 bb bb l.ori r9,0xbbbb
1438 * where 0xaaaabbbb is EEA + 0x4 shifted right 2
1441 l.addi r6,r2,0x4 // this is 0xaaaabbbb
1443 // l.movhi r9,0xaaaa
1444 l.ori r5,r0,0x1920 // 0x1920 == l.movhi r9
1445 l.sh (TRAMP_SLOT_0+0x0)(r3),r5
1447 l.sh (TRAMP_SLOT_0+0x2)(r3),r5
1449 // l.ori r9,0xbbbb
1450 l.ori r5,r0,0xa929 // 0xa929 == l.ori r9
1451 l.sh (TRAMP_SLOT_1+0x0)(r3),r5
1452 l.andi r5,r6,0xffff
1453 l.sh (TRAMP_SLOT_1+0x2)(r3),r5
1455 l.lhz r5,(TRAMP_SLOT_2+0x0)(r3) // load hi part of jump instruction
1456 l.andi r5,r5,0x3ff // clear out opcode part
1457 l.ori r5,r5,0x4400 // opcode changed from l.jalr -> l.jr
1458 l.sh (TRAMP_SLOT_2+0x0)(r3),r5 // write it back
1476 l.addi r5,r3,0xc // new jump position (physical)
1487 l.lwz r4,(TRAMP_SLOT_2+0x0)(r3) // load jump instruction
1489 l.andi r4,r4,0xfc00 // get opcode part
1494 /* we need to add l.j to EEA + 0x8 */
1496 l.addi r4,r4,(0x8 - 0x8) // jump target = r2 + 0x8 (compensate for 0x8)
1497 // jump position = r5 + 0x8 (0x8 compensated)
1498 l.sub r4,r4,r5 // jump offset = target - new_position + 0x8
1516 If BS=0, 16;
1550 l.lbz r7,0(r3)
1558 l.addi r6,r0,0x20
1560 l.andi r5,r5,0x20
1565 l.sb 0(r4),r7
1567 l.addi r6,r0,0x60
1569 l.andi r5,r5,0x60
1576 l.addi r3,r3,0x1
1596 l.addi r8,r8,-0x4
1598 l.andi r7,r7,0xf
1600 /* don't skip the last zero if number == 0x0 */
1601 l.sfeqi r8,0x4
1612 l.andi r7,r7,0xf
1616 l.sfgtui r7,0x9
1619 l.addi r7,r7,0x27
1622 l.addi r7,r7,0x30
1626 l.addi r6,r0,0x20
1628 l.andi r5,r5,0x20
1633 l.sb 0(r4),r7
1635 l.addi r6,r0,0x60
1637 l.andi r5,r5,0x60
1644 l.addi r8,r8,-0x4
1680 l.addi r4,r0,0x7
1681 l.sb 0x2(r3),r4
1683 l.addi r4,r0,0x0
1684 l.sb 0x1(r3),r4
1686 l.addi r4,r0,0x3
1687 l.sb 0x3(r3),r4
1690 l.ori r4,r5,0x80
1691 l.sb 0x3(r3),r4
1692 l.addi r4,r0,((UART_DIVISOR>>8) & 0x000000ff)
1694 l.addi r4,r0,((UART_DIVISOR) & 0x000000ff)
1696 l.sb 0x3(r3),r5
1701 .align 0x1000
1705 .space 0x800
1714 .string "\n\rRunarunaround: Unhandled exception 0x\0"
1717 .string ": EPC=0x\0"
1720 .string "\n\r\0"