Lines Matching +full:way +full:- +full:select

1 # SPDX-License-Identifier: GPL-2.0-only
50 	  A set of Zero-Overhead Loop mechanism is provided to reduce the
51 	  instruction fetch and execution overhead of loop-control instructions.
63 	  If this CPU is using VIPT data cache and its cache way size is larger
75 	  if its cache way size is larger than page size. You can specify the
88 	select CPU_CACHE_ALIASING if ANDES_PAGE_SIZE_4KB
91 	select CPU_CACHE_ALIASING
96 	select CPU_CACHE_ALIASING
99 	select CPU_CACHE_ALIASING
102 	prompt "Paging -- page size "
111 	bool "Disable I-Cache"
117 	bool "Disable D-Cache"
123 	bool "Force write through D-cache"
133 	  Say Y here to enable write-back memory with no-write-allocation policy.
142 	  address divisible by 4. On 32-bit Andes processors, these non-aligned
144 	  here, which has a severe performance impact. With an IP-only
152 	  Andes processors load/store world/half-word instructions can access
154 	  Check exceptions. With an IP-only configuration it is safe to say N,
160 	select KMAP_LOCAL
196 	  Select the desired split between kernel and user memory.