Lines Matching +full:0 +full:x900
52 #define SATA_CTL 0x0
53 #define SATA_STATUS 0x1 /* Status Reg */
54 #define SATA_INT 0x2 /* Interrupt Reg */
55 #define SATA_INT_MASK 0x3 /* Interrupt Mask Reg */
56 #define SATA_CR_REG_TIMER 0x4 /* PHY Conrol Timer Reg */
57 #define SATA_CORE_ID 0x5 /* Core ID Reg */
58 #define SATA_AXI_SLAVE_OPT1 0x6 /* AXI Slave Options Reg */
59 #define SATA_PHY_LOS_LEV 0x7 /* PHY LOS Level Reg */
60 #define SATA_PHY_MULTI 0x8 /* PHY Multiplier Reg */
61 #define SATA_PHY_CLK_SEL 0x9 /* Clock Select Reg */
62 #define SATA_PHY_AMP1_GEN1 0xa /* PHY Transmit Amplitude Reg 1 */
63 #define SATA_PHY_AMP1_GEN2 0xb /* PHY Transmit Amplitude Reg 2 */
64 #define SATA_PHY_AMP1_GEN3 0xc /* PHY Transmit Amplitude Reg 3 */
65 #define SATA_PHY_PRE1 0xd /* PHY Transmit Preemphasis Reg 1 */
66 #define SATA_PHY_PRE2 0xe /* PHY Transmit Preemphasis Reg 2 */
67 #define SATA_PHY_PRE3 0xf /* PHY Transmit Preemphasis Reg 3 */
68 #define SATA_SPDMODE 0x10 /* Speed Mode Reg */
69 #define SATA_REFCLK 0x11 /* Reference Clock Control Reg */
70 #define SATA_BYTE_SWAP_DIS 0x12 /* byte swap disable */
73 #define SATA_RST_N BIT(0)
91 /* SATA device specific configuration registers are starts at 0x900 offset */
93 (nlm_get_sata_pcibase(node) + 0x900)
135 i = 0; in nlm_sata_firmware_init()
139 } while (((reg_val & 0xF0) != 0xF0) && (i < 10000)); in nlm_sata_firmware_init()
141 for (i = 0; i < 4; i++) { in nlm_sata_firmware_init()
153 int node = 0; in nlm_ahci_init()
158 return 0; in nlm_ahci_init()
163 uint32_t val = 0; in nlm_sata_intr_ack()
174 * The AHCI resource is in BAR 0, move it to in nlm_sata_fixup_bar()
177 dev->resource[5] = dev->resource[0]; in nlm_sata_fixup_bar()
178 memset(&dev->resource[0], 0, sizeof(dev->resource[0])); in nlm_sata_fixup_bar()
185 int node = 0; /* XLP3XX does not support multi-node */ in nlm_sata_fixup_final()
198 sata_set_glue_reg(regbase, SATA_INT_MASK, 0x1); in nlm_sata_fixup_final()