Lines Matching +full:d +full:- +full:cache +full:- +full:sets
22 #include <linux/dma-map-ops.h> /* for dma_default_coherent */
26 #include <asm/cache.h>
29 #include <asm/cpu-features.h>
30 #include <asm/cpu-type.h>
39 #include <asm/mips-cps.h>
42 * Bits describing what cache ops an SMP callback function may perform.
44 * R4K_HIT - Virtual user or kernel address based cache operations. The
47 * R4K_INDEX - Index based cache operations.
54 * r4k_op_needs_ipi() - Decide if a cache op needs to be done on every core.
55 * @type: Type of cache operations (R4K_HIT or R4K_INDEX).
57 * Decides whether a cache op needs to be performed on every core in the system.
58 * This may change depending on the @type of cache operation, as well as the set
62 * Returns: 1 if the cache operation @type should be done on every core in
64 * 0 if the cache operation @type is globalized and only needs to
69 /* The MIPS Coherence Manager (CM) globalizes address-based cache ops */ in r4k_op_needs_ipi()
74 * Hardware doesn't globalize the required cache ops, so SMP calls may in r4k_op_needs_ipi()
75 * be needed, but only if there are foreign CPUs (non-siblings with in r4k_op_needs_ipi()
87 * Special Variant of smp_call_function for use by cache functions:
92 * primary cache.
115 * Dummy cache handling routines for machines without boardcaches
295 unsigned long indexmask = current_cpu_data.icache.waysize - 1; in tx49_blast_icache32_page_indexed()
500 * is not cached in the S-cache, we know it also won't be in local_r4k___flush_cache_all()
529 * has_valid_asid() - Determine if an mm already has an ASID.
531 * @type: R4K_HIT or R4K_INDEX, type of cache op.
533 * Determines whether @mm already has an ASID on any of the CPUs which cache ops
539 * Must be called in non-preemptive context.
541 * Returns: 1 if the CPUs affected by @type cache ops have an ASID for @mm.
585 int exec = vma->vm_flags & VM_EXEC; in local_r4k_flush_cache_range()
587 if (!has_valid_asid(vma->vm_mm, R4K_INDEX)) in local_r4k_flush_cache_range()
605 int exec = vma->vm_flags & VM_EXEC; in r4k_flush_cache_range()
621 * R4000SC and R4400SC indexed S-cache ops also invalidate primary in local_r4k_flush_cache_mm()
652 struct vm_area_struct *vma = fcp_args->vma; in local_r4k_flush_cache_page()
653 unsigned long addr = fcp_args->addr; in local_r4k_flush_cache_page()
654 struct page *page = pfn_to_page(fcp_args->pfn); in local_r4k_flush_cache_page()
655 int exec = vma->vm_flags & VM_EXEC; in local_r4k_flush_cache_page()
656 struct mm_struct *mm = vma->vm_mm; in local_r4k_flush_cache_page()
664 * this page into the cache. in local_r4k_flush_cache_page()
675 * in the cache. in local_r4k_flush_cache_page()
680 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) in local_r4k_flush_cache_page()
704 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) { in local_r4k_flush_cache_page()
759 (type & R4K_INDEX && end - start >= dcache_size)) { in __local_r4k_flush_icache_range()
771 (type & R4K_INDEX && end - start > icache_size)) in __local_r4k_flush_icache_range()
804 unsigned long start = fir_args->start; in local_r4k_flush_icache_range_ipi()
805 unsigned long end = fir_args->end; in local_r4k_flush_icache_range_ipi()
806 unsigned int type = fir_args->type; in local_r4k_flush_icache_range_ipi()
807 bool user = fir_args->user; in local_r4k_flush_icache_range_ipi()
824 * Indexed cache ops require an SMP call. in __r4k_flush_icache_range()
830 * If address-based cache ops don't require an SMP call, then in __r4k_flush_icache_range()
833 size = end - start; in __r4k_flush_icache_range()
881 * Either no secondary cache or the available caches don't have the in r4k_dma_cache_wback_inv()
884 * If we would need IPI to perform an INDEX-type operation, then in r4k_dma_cache_wback_inv()
885 * we have to use the HIT-type alternative as IPI cannot be used in r4k_dma_cache_wback_inv()
905 addr0 &= ~(linesz - 1); in prefetch_cache_inv()
906 addr1 = (addr0 + size - 1) & ~(linesz - 1); in prefetch_cache_inv()
920 addr1 -= linesz; in prefetch_cache_inv()
945 * for the cache instruction on MIPS processors and in r4k_dma_cache_inv()
947 * QED processors will throw an address error for cache in r4k_dma_cache_inv()
949 * aligning the address to cache line size. in r4k_dma_cache_inv()
986 * S-caches or T-caches. in local_r4k_flush_kernel_vmap_range_index()
994 unsigned long vaddr = vmra->vaddr; in local_r4k_flush_kernel_vmap_range()
995 int size = vmra->size; in local_r4k_flush_kernel_vmap_range()
999 * S-caches or T-caches. in local_r4k_flush_kernel_vmap_range()
1034 "cache\t%1, 0(%0)\n\t" in rm7k_erratum31()
1035 "cache\t%1, 0x1000(%0)\n\t" in rm7k_erratum31()
1036 "cache\t%1, 0x2000(%0)\n\t" in rm7k_erratum31()
1037 "cache\t%1, 0x3000(%0)\n\t" in rm7k_erratum31()
1038 "cache\t%2, 0(%0)\n\t" in rm7k_erratum31()
1039 "cache\t%2, 0x1000(%0)\n\t" in rm7k_erratum31()
1040 "cache\t%2, 0x2000(%0)\n\t" in rm7k_erratum31()
1041 "cache\t%2, 0x3000(%0)\n\t" in rm7k_erratum31()
1042 "cache\t%1, 0(%0)\n\t" in rm7k_erratum31()
1043 "cache\t%1, 0x1000(%0)\n\t" in rm7k_erratum31()
1044 "cache\t%1, 0x2000(%0)\n\t" in rm7k_erratum31()
1045 "cache\t%1, 0x3000(%0)\n\t" in rm7k_erratum31()
1054 unsigned int imp = c->processor_id & PRID_IMP_MASK; in alias_74k_erratum()
1055 unsigned int rev = c->processor_id & PRID_REV_MASK; in alias_74k_erratum()
1059 * Early versions of the 74K do not update the cache tags on a in alias_74k_erratum()
1061 * aliases. In this case it is better to treat the cache as always in alias_74k_erratum()
1065 * address hit during a D-cache look-up. in alias_74k_erratum()
1099 static char *way_string[] = { NULL, "direct mapped", "2-way",
1100 "3-way", "4-way", "5-way", "6-way", "7-way", "8-way",
1101 "9-way", "10-way", "11-way", "12-way",
1102 "13-way", "14-way", "15-way", "16-way",
1120 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); in probe_pcache()
1121 c->icache.ways = 2; in probe_pcache()
1122 c->icache.waybit = __ffs(icache_size/2); in probe_pcache()
1125 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); in probe_pcache()
1126 c->dcache.ways = 2; in probe_pcache()
1127 c->dcache.waybit= __ffs(dcache_size/2); in probe_pcache()
1129 c->options |= MIPS_CPU_CACHE_CDEX_P; in probe_pcache()
1134 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); in probe_pcache()
1135 c->icache.ways = 2; in probe_pcache()
1136 c->icache.waybit= 0; in probe_pcache()
1139 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); in probe_pcache()
1140 c->dcache.ways = 2; in probe_pcache()
1141 c->dcache.waybit = 0; in probe_pcache()
1143 c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH; in probe_pcache()
1148 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); in probe_pcache()
1149 c->icache.ways = 4; in probe_pcache()
1150 c->icache.waybit= 0; in probe_pcache()
1153 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); in probe_pcache()
1154 c->dcache.ways = 4; in probe_pcache()
1155 c->dcache.waybit = 0; in probe_pcache()
1157 c->options |= MIPS_CPU_CACHE_CDEX_P; in probe_pcache()
1158 c->options |= MIPS_CPU_PREFETCH; in probe_pcache()
1169 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); in probe_pcache()
1170 c->icache.ways = 1; in probe_pcache()
1171 c->icache.waybit = 0; /* doesn't matter */ in probe_pcache()
1174 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); in probe_pcache()
1175 c->dcache.ways = 1; in probe_pcache()
1176 c->dcache.waybit = 0; /* does not matter */ in probe_pcache()
1178 c->options |= MIPS_CPU_CACHE_CDEX_P; in probe_pcache()
1186 c->icache.linesz = 64; in probe_pcache()
1187 c->icache.ways = 2; in probe_pcache()
1188 c->icache.waybit = 0; in probe_pcache()
1191 c->dcache.linesz = 32; in probe_pcache()
1192 c->dcache.ways = 2; in probe_pcache()
1193 c->dcache.waybit = 0; in probe_pcache()
1195 c->options |= MIPS_CPU_PREFETCH; in probe_pcache()
1202 /* Workaround for cache instruction bug of VR4131 */ in probe_pcache()
1203 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U || in probe_pcache()
1204 c->processor_id == 0x0c82U) { in probe_pcache()
1206 if (c->processor_id == 0x0c80U) in probe_pcache()
1210 c->options |= MIPS_CPU_CACHE_CDEX_P; in probe_pcache()
1213 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); in probe_pcache()
1214 c->icache.ways = 2; in probe_pcache()
1215 c->icache.waybit = __ffs(icache_size/2); in probe_pcache()
1218 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); in probe_pcache()
1219 c->dcache.ways = 2; in probe_pcache()
1220 c->dcache.waybit = __ffs(dcache_size/2); in probe_pcache()
1230 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); in probe_pcache()
1231 c->icache.ways = 1; in probe_pcache()
1232 c->icache.waybit = 0; /* doesn't matter */ in probe_pcache()
1235 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); in probe_pcache()
1236 c->dcache.ways = 1; in probe_pcache()
1237 c->dcache.waybit = 0; /* does not matter */ in probe_pcache()
1239 c->options |= MIPS_CPU_CACHE_CDEX_P; in probe_pcache()
1246 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); in probe_pcache()
1247 c->icache.ways = 4; in probe_pcache()
1248 c->icache.waybit = __ffs(icache_size / c->icache.ways); in probe_pcache()
1251 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); in probe_pcache()
1252 c->dcache.ways = 4; in probe_pcache()
1253 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways); in probe_pcache()
1255 c->options |= MIPS_CPU_CACHE_CDEX_P; in probe_pcache()
1256 c->options |= MIPS_CPU_PREFETCH; in probe_pcache()
1261 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); in probe_pcache()
1263 c->icache.ways = 4; in probe_pcache()
1265 c->icache.ways = 2; in probe_pcache()
1266 c->icache.waybit = 0; in probe_pcache()
1269 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); in probe_pcache()
1271 c->dcache.ways = 4; in probe_pcache()
1273 c->dcache.ways = 2; in probe_pcache()
1274 c->dcache.waybit = 0; in probe_pcache()
1281 c->icache.linesz = 2 << lsize; in probe_pcache()
1283 c->icache.linesz = 0; in probe_pcache()
1284 c->icache.sets = 64 << ((config1 >> 22) & 7); in probe_pcache()
1285 c->icache.ways = 1 + ((config1 >> 16) & 7); in probe_pcache()
1286 icache_size = c->icache.sets * in probe_pcache()
1287 c->icache.ways * in probe_pcache()
1288 c->icache.linesz; in probe_pcache()
1289 c->icache.waybit = 0; in probe_pcache()
1293 c->dcache.linesz = 2 << lsize; in probe_pcache()
1295 c->dcache.linesz = 0; in probe_pcache()
1296 c->dcache.sets = 64 << ((config1 >> 13) & 7); in probe_pcache()
1297 c->dcache.ways = 1 + ((config1 >> 7) & 7); in probe_pcache()
1298 dcache_size = c->dcache.sets * in probe_pcache()
1299 c->dcache.ways * in probe_pcache()
1300 c->dcache.linesz; in probe_pcache()
1301 c->dcache.waybit = 0; in probe_pcache()
1302 if ((c->processor_id & (PRID_IMP_MASK | PRID_REV_MASK)) >= in probe_pcache()
1304 (c->processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64R) in probe_pcache()
1305 c->options |= MIPS_CPU_PREFETCH; in probe_pcache()
1310 c->icache.linesz = 128; in probe_pcache()
1311 c->icache.sets = 16; in probe_pcache()
1312 c->icache.ways = 8; in probe_pcache()
1313 c->icache.flags |= MIPS_CACHE_VTAG; in probe_pcache()
1314 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz; in probe_pcache()
1316 c->dcache.linesz = 128; in probe_pcache()
1317 c->dcache.ways = 8; in probe_pcache()
1318 c->dcache.sets = 8; in probe_pcache()
1319 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; in probe_pcache()
1320 c->options |= MIPS_CPU_PREFETCH; in probe_pcache()
1325 panic("Don't know how to probe P-caches on this cpu."); in probe_pcache()
1329 * So let's probe the I-cache ... in probe_pcache()
1339 c->icache.linesz = lsize ? 2 << lsize : 0; in probe_pcache()
1341 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); in probe_pcache()
1342 c->icache.ways = 1 + ((config1 >> 16) & 7); in probe_pcache()
1344 icache_size = c->icache.sets * in probe_pcache()
1345 c->icache.ways * in probe_pcache()
1346 c->icache.linesz; in probe_pcache()
1347 c->icache.waybit = __ffs(icache_size/c->icache.ways); in probe_pcache()
1350 c->icache.flags |= MIPS_CACHE_VTAG; in probe_pcache()
1353 * Now probe the MIPS32 / MIPS64 data cache. in probe_pcache()
1355 c->dcache.flags = 0; in probe_pcache()
1363 c->dcache.linesz = lsize ? 2 << lsize : 0; in probe_pcache()
1365 c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7); in probe_pcache()
1366 c->dcache.ways = 1 + ((config1 >> 7) & 7); in probe_pcache()
1368 dcache_size = c->dcache.sets * in probe_pcache()
1369 c->dcache.ways * in probe_pcache()
1370 c->dcache.linesz; in probe_pcache()
1371 c->dcache.waybit = __ffs(dcache_size/c->dcache.ways); in probe_pcache()
1373 c->options |= MIPS_CPU_PREFETCH; in probe_pcache()
1387 !(config & CONF_SC) && c->icache.linesz != 16 && in probe_pcache()
1391 /* compute a couple of other cache variables */ in probe_pcache()
1392 c->icache.waysize = icache_size / c->icache.ways; in probe_pcache()
1393 c->dcache.waysize = dcache_size / c->dcache.ways; in probe_pcache()
1395 c->icache.sets = c->icache.linesz ? in probe_pcache()
1396 icache_size / (c->icache.linesz * c->icache.ways) : 0; in probe_pcache()
1397 c->dcache.sets = c->dcache.linesz ? in probe_pcache()
1398 dcache_size / (c->dcache.linesz * c->dcache.ways) : 0; in probe_pcache()
1401 * R1x000 P-caches are odd in a positive way. They're 32kB 2-way in probe_pcache()
1403 * normally they'd suffer from aliases but magic in the hardware deals in probe_pcache()
1414 c->dcache.flags |= MIPS_CACHE_PINDEX; in probe_pcache()
1440 (c->icache.waysize > PAGE_SIZE)) in probe_pcache()
1441 c->icache.flags |= MIPS_CACHE_ALIASES; in probe_pcache()
1447 c->dcache.flags |= MIPS_CACHE_PINDEX; in probe_pcache()
1452 if (has_74k_erratum || c->dcache.waysize > PAGE_SIZE) in probe_pcache()
1453 c->dcache.flags |= MIPS_CACHE_ALIASES; in probe_pcache()
1457 if (c->dcache.flags & MIPS_CACHE_PINDEX) in probe_pcache()
1458 c->dcache.flags &= ~MIPS_CACHE_ALIASES; in probe_pcache()
1466 c->icache.flags |= MIPS_IC_SNOOPS_REMOTE; in probe_pcache()
1474 c->icache.flags |= MIPS_CACHE_VTAG; in probe_pcache()
1480 c->icache.flags |= MIPS_CACHE_IC_F_DC; in probe_pcache()
1484 c->icache.flags |= MIPS_CACHE_IC_F_DC; in probe_pcache()
1485 /* Cache aliases are handled in hardware; allow HIGHMEM */ in probe_pcache()
1486 c->dcache.flags &= ~MIPS_CACHE_ALIASES; in probe_pcache()
1491 * LOONGSON2 has 4 way icache, but when using indexed cache op, in probe_pcache()
1494 c->icache.ways = 1; in probe_pcache()
1497 pr_info("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", in probe_pcache()
1499 c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT", in probe_pcache()
1500 way_string[c->icache.ways], c->icache.linesz); in probe_pcache()
1502 pr_info("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n", in probe_pcache()
1503 dcache_size >> 10, way_string[c->dcache.ways], in probe_pcache()
1504 (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT", in probe_pcache()
1505 (c->dcache.flags & MIPS_CACHE_ALIASES) ? in probe_pcache()
1506 "cache aliases" : "no aliases", in probe_pcache()
1507 c->dcache.linesz); in probe_pcache()
1520 c->vcache.linesz = 2 << lsize; in probe_vcache()
1522 c->vcache.linesz = lsize; in probe_vcache()
1524 c->vcache.sets = 64 << ((config2 >> 24) & 15); in probe_vcache()
1525 c->vcache.ways = 1 + ((config2 >> 16) & 15); in probe_vcache()
1527 vcache_size = c->vcache.sets * c->vcache.ways * c->vcache.linesz; in probe_vcache()
1529 c->vcache.waybit = 0; in probe_vcache()
1530 c->vcache.waysize = vcache_size / c->vcache.ways; in probe_vcache()
1532 pr_info("Unified victim cache %ldkB %s, linesize %d bytes.\n", in probe_vcache()
1533 vcache_size >> 10, way_string[c->vcache.ways], c->vcache.linesz); in probe_vcache()
1538 * it does not pop things on and off the stack for the cache sizing loop that
1552 begin &= ~((4 * 1024 * 1024) - 1); in probe_scache()
1556 * This is such a bitch, you'd think they would make it easy to do in probe_scache()
1561 /* Fill each size-multiple cache line with a valid tag. */ in probe_scache()
1587 addr -= begin; in probe_scache()
1590 c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22); in probe_scache()
1591 c->scache.ways = 1; in probe_scache()
1592 c->scache.waybit = 0; /* does not matter */ in probe_scache()
1602 c->scache.linesz = 32; in loongson2_sc_init()
1603 c->scache.ways = 4; in loongson2_sc_init()
1604 c->scache.waybit = 0; in loongson2_sc_init()
1605 c->scache.waysize = scache_size / (c->scache.ways); in loongson2_sc_init()
1606 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); in loongson2_sc_init()
1607 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n", in loongson2_sc_init()
1608 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); in loongson2_sc_init()
1610 c->options |= MIPS_CPU_INCLUSIVE_CACHES; in loongson2_sc_init()
1621 c->scache.linesz = 2 << lsize; in loongson3_sc_init()
1623 c->scache.linesz = 0; in loongson3_sc_init()
1624 c->scache.sets = 64 << ((config2 >> 8) & 15); in loongson3_sc_init()
1625 c->scache.ways = 1 + (config2 & 15); in loongson3_sc_init()
1627 /* Loongson-3 has 4-Scache banks, while Loongson-2K have only 2 banks */ in loongson3_sc_init()
1628 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64R) in loongson3_sc_init()
1629 c->scache.sets *= 2; in loongson3_sc_init()
1631 c->scache.sets *= 4; in loongson3_sc_init()
1633 scache_size = c->scache.sets * c->scache.ways * c->scache.linesz; in loongson3_sc_init()
1635 c->scache.waybit = 0; in loongson3_sc_init()
1636 c->scache.waysize = scache_size / c->scache.ways; in loongson3_sc_init()
1637 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n", in loongson3_sc_init()
1638 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); in loongson3_sc_init()
1640 c->options |= MIPS_CPU_INCLUSIVE_CACHES; in loongson3_sc_init()
1656 * processors don't have a S-cache that would be relevant to the in setup_scache()
1666 c->options |= MIPS_CPU_CACHE_CDEX_S; in setup_scache()
1674 c->scache.linesz = 64 << ((config >> 13) & 1); in setup_scache()
1675 c->scache.ways = 2; in setup_scache()
1676 c->scache.waybit= 0; in setup_scache()
1707 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | in setup_scache()
1713 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz; in setup_scache()
1714 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n", in setup_scache()
1716 way_string[c->scache.ways], c->scache.linesz); in setup_scache()
1719 c->options |= MIPS_CPU_INCLUSIVE_CACHES; in setup_scache()
1723 if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT)) in setup_scache()
1724 panic("Dunno how to handle MIPS32 / MIPS64 second level cache"); in setup_scache()
1734 /* compute a couple of other cache variables */ in setup_scache()
1735 c->scache.waysize = scache_size / c->scache.ways; in setup_scache()
1737 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); in setup_scache()
1739 printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n", in setup_scache()
1740 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); in setup_scache()
1742 c->options |= MIPS_CPU_INCLUSIVE_CACHES; in setup_scache()
1783 /* clear all three cache coherency fields */ in nxp_pr4450_fixup_config()
1792 static int cca = -1;
1809 pr_debug("Using cache attribute %d\n", cca); in coherency_setup()
1830 * the write-only co_config.od bit and set it back to one on: in coherency_setup()
1890 if (c->dcache.linesz && cpu_has_dc_aliases) in r4k_cache_init()
1892 c->dcache.sets * c->dcache.linesz - 1, in r4k_cache_init()
1893 PAGE_SIZE - 1); in r4k_cache_init()
1895 shm_align_mask = PAGE_SIZE-1; in r4k_cache_init()
1942 * Per-CPU overrides in r4k_cache_init()
1947 /* No IPI is needed because all CPUs share the same D$ */ in r4k_cache_init()
1952 if (c->scache.flags & MIPS_CACHE_NOT_PRESENT) in r4k_cache_init()
1955 /* I$ fills from D$ just by emptying the write buffers */ in r4k_cache_init()
1968 /* Loongson-3 maintains cache coherency by hardware */ in r4k_cache_init()