6  * Copyright (C) 2005-2007 Cavium Networks
20 #include <asm/cpu-features.h>
21 #include <asm/cpu-type.h>
34  * Octeon automatically flushes the dcache on tlb changes, so
50  * Flush local I-cache for the specified range.
59  * octeon_flush_icache_all_cores -  Flush caches as necessary for all cores
83 		mask = *mm_cpumask(vma->vm_mm);  in octeon_flush_icache_all_cores()
105  * octeon_flush_cache_mm - flush all memory associated with a memory context.
129  * octeon_flush_cache_range - Flush a range out of a vma
138 	if (vma->vm_flags & VM_EXEC)  in octeon_flush_cache_range()
144  * octeon_flush_cache_page - Flush a specific page of a vma
153 	if (vma->vm_flags & VM_EXEC)  in octeon_flush_cache_page()
178 		c->icache.linesz = 2 << ((config1 >> 19) & 7);  in probe_octeon()
179 		c->icache.sets = 64 << ((config1 >> 22) & 7);  in probe_octeon()
180 		c->icache.ways = 1 + ((config1 >> 16) & 7);  in probe_octeon()
181 		c->icache.flags |= MIPS_CACHE_VTAG;  in probe_octeon()
183 			c->icache.sets * c->icache.ways * c->icache.linesz;  in probe_octeon()
184 		c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;  in probe_octeon()
185 		c->dcache.linesz = 128;  in probe_octeon()
187 			c->dcache.sets = 2; /* CN5XXX has two Dcache sets */  in probe_octeon()
189 			c->dcache.sets = 1; /* CN3XXX has one Dcache set */  in probe_octeon()
190 		c->dcache.ways = 64;  in probe_octeon()
192 			c->dcache.sets * c->dcache.ways * c->dcache.linesz;  in probe_octeon()
193 		c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1;  in probe_octeon()
194 		c->options |= MIPS_CPU_PREFETCH;  in probe_octeon()
198 		c->icache.linesz = 2 << ((config1 >> 19) & 7);  in probe_octeon()
199 		c->icache.sets = 8;  in probe_octeon()
200 		c->icache.ways = 37;  in probe_octeon()
201 		c->icache.flags |= MIPS_CACHE_VTAG;  in probe_octeon()
202 		icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;  in probe_octeon()
204 		c->dcache.linesz = 128;  in probe_octeon()
205 		c->dcache.ways = 32;  in probe_octeon()
206 		c->dcache.sets = 8;  in probe_octeon()
207 		dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;  in probe_octeon()
208 		c->options |= MIPS_CPU_PREFETCH;  in probe_octeon()
212 		c->icache.linesz = 128;  in probe_octeon()
213 		c->icache.sets = 16;  in probe_octeon()
214 		c->icache.ways = 39;  in probe_octeon()
215 		c->icache.flags |= MIPS_CACHE_VTAG;  in probe_octeon()
216 		icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;  in probe_octeon()
218 		c->dcache.linesz = 128;  in probe_octeon()
219 		c->dcache.ways = 32;  in probe_octeon()
220 		c->dcache.sets = 8;  in probe_octeon()
221 		dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;  in probe_octeon()
222 		c->options |= MIPS_CPU_PREFETCH;  in probe_octeon()
231 	c->icache.waysize = icache_size / c->icache.ways;  in probe_octeon()
232 	c->dcache.waysize = dcache_size / c->dcache.ways;  in probe_octeon()
234 	c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways);  in probe_octeon()
235 	c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways);  in probe_octeon()
238 		pr_info("Primary instruction cache %ldkB, %s, %d way, "  in probe_octeon()
239 			"%d sets, linesize %d bytes.\n",  in probe_octeon()
243 			c->icache.ways, c->icache.sets, c->icache.linesz);  in probe_octeon()
245 		pr_info("Primary data cache %ldkB, %d-way, %d sets, "  in probe_octeon()
246 			"linesize %d bytes.\n",  in probe_octeon()
247 			dcache_size >> 10, c->dcache.ways,  in probe_octeon()
248 			c->dcache.sets, c->dcache.linesz);  in probe_octeon()
266 	shm_align_mask = PAGE_SIZE - 1;  in octeon_cache_init()