Lines Matching refs:T0

31 #define T0		8  macro
38 #define T0 12 macro
305 UASM_i_LW(&p, T0, offsetof(struct kvm_vcpu_arch, pc), K1); in kvm_mips_build_enter_guest()
306 UASM_i_MTC0(&p, T0, C0_EPC); in kvm_mips_build_enter_guest()
347 uasm_i_mfc0(&p, T0, C0_GUESTCTL1); in kvm_mips_build_enter_guest()
349 uasm_i_ext(&p, T1, T0, MIPS_GCTL1_ID_SHIFT, in kvm_mips_build_enter_guest()
351 uasm_i_ins(&p, T0, T1, MIPS_GCTL1_RID_SHIFT, in kvm_mips_build_enter_guest()
353 uasm_i_mtc0(&p, T0, C0_GUESTCTL1); in kvm_mips_build_enter_guest()
601 uasm_i_mfhi(&p, T0); in kvm_mips_build_exit()
602 UASM_i_SW(&p, T0, offsetof(struct kvm_vcpu_arch, hi), K1); in kvm_mips_build_exit()
604 uasm_i_mflo(&p, T0); in kvm_mips_build_exit()
605 UASM_i_SW(&p, T0, offsetof(struct kvm_vcpu_arch, lo), K1); in kvm_mips_build_exit()
610 UASM_i_MFC0(&p, T0, scratch_tmp[0], scratch_tmp[1]); in kvm_mips_build_exit()
611 UASM_i_SW(&p, T0, offsetof(struct kvm_vcpu_arch, gprs[K1]), K1); in kvm_mips_build_exit()
669 uasm_i_cfc1(&p, T0, 31); in kvm_mips_build_exit()
670 uasm_i_sw(&p, T0, offsetof(struct kvm_vcpu_arch, fpu.fcr31), in kvm_mips_build_exit()
681 uasm_i_mfc0(&p, T0, C0_CONFIG5); in kvm_mips_build_exit()
682 uasm_i_ext(&p, T0, T0, 27, 1); /* MIPS_CONF5_MSAEN */ in kvm_mips_build_exit()
683 uasm_il_beqz(&p, &r, T0, label_msa_1); in kvm_mips_build_exit()
685 uasm_i_cfcmsa(&p, T0, MSA_CSR); in kvm_mips_build_exit()
686 uasm_i_sw(&p, T0, offsetof(struct kvm_vcpu_arch, fpu.msacsr), in kvm_mips_build_exit()
729 uasm_i_mfc0(&p, T0, C0_GUESTCTL1); in kvm_mips_build_exit()
731 uasm_i_ins(&p, T0, ZERO, MIPS_GCTL1_RID_SHIFT, in kvm_mips_build_exit()
733 uasm_i_mtc0(&p, T0, C0_GUESTCTL1); in kvm_mips_build_exit()
824 uasm_i_andi(&p, T0, V0, RESUME_HOST); in kvm_mips_build_ret_from_exit()
825 uasm_il_bnez(&p, &r, T0, label_return_to_host); in kvm_mips_build_ret_from_exit()
855 UASM_i_LW(&p, T0, offsetof(struct kvm_vcpu_arch, guest_ebase), K1); in kvm_mips_build_ret_to_guest()
863 build_set_exc_base(&p, T0); in kvm_mips_build_ret_to_guest()