Lines Matching +full:reg +full:- +full:addr
18 * only the performance is affected. Much worse is that such code is non-
30 * option in your user programs - I discourage the use of the software
31 * emulation strongly - use the following code in your userland stuff:
92 #include <asm/unaligned-emul.h>
96 #include "access-helper.h"
112 void __user *addr, unsigned int *pc) in emulate_load_store_insn() argument
120 orig31 = regs->regs[31]; in emulate_load_store_insn()
132 * can assume therefore that the code is MIPS-aware and in emulate_load_store_insn()
167 if (user && !access_ok(addr, 4)) in emulate_load_store_insn()
169 LoadW(addr, value, res); in emulate_load_store_insn()
173 regs->regs[insn.dsp_format.rd] = value; in emulate_load_store_insn()
176 if (user && !access_ok(addr, 2)) in emulate_load_store_insn()
178 LoadHW(addr, value, res); in emulate_load_store_insn()
182 regs->regs[insn.dsp_format.rd] = value; in emulate_load_store_insn()
197 if (!access_ok(addr, 2)) in emulate_load_store_insn()
199 LoadHWE(addr, value, res); in emulate_load_store_insn()
203 regs->regs[insn.spec3_format.rt] = value; in emulate_load_store_insn()
206 if (!access_ok(addr, 4)) in emulate_load_store_insn()
208 LoadWE(addr, value, res); in emulate_load_store_insn()
212 regs->regs[insn.spec3_format.rt] = value; in emulate_load_store_insn()
215 if (!access_ok(addr, 2)) in emulate_load_store_insn()
217 LoadHWUE(addr, value, res); in emulate_load_store_insn()
221 regs->regs[insn.spec3_format.rt] = value; in emulate_load_store_insn()
224 if (!access_ok(addr, 2)) in emulate_load_store_insn()
227 value = regs->regs[insn.spec3_format.rt]; in emulate_load_store_insn()
228 StoreHWE(addr, value, res); in emulate_load_store_insn()
233 if (!access_ok(addr, 4)) in emulate_load_store_insn()
236 value = regs->regs[insn.spec3_format.rt]; in emulate_load_store_insn()
237 StoreWE(addr, value, res); in emulate_load_store_insn()
248 if (user && !access_ok(addr, 2)) in emulate_load_store_insn()
252 LoadHWE(addr, value, res); in emulate_load_store_insn()
254 LoadHW(addr, value, res); in emulate_load_store_insn()
259 regs->regs[insn.i_format.rt] = value; in emulate_load_store_insn()
263 if (user && !access_ok(addr, 4)) in emulate_load_store_insn()
267 LoadWE(addr, value, res); in emulate_load_store_insn()
269 LoadW(addr, value, res); in emulate_load_store_insn()
274 regs->regs[insn.i_format.rt] = value; in emulate_load_store_insn()
278 if (user && !access_ok(addr, 2)) in emulate_load_store_insn()
282 LoadHWUE(addr, value, res); in emulate_load_store_insn()
284 LoadHWU(addr, value, res); in emulate_load_store_insn()
289 regs->regs[insn.i_format.rt] = value; in emulate_load_store_insn()
295 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_insn()
296 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_insn()
297 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_insn()
298 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_insn()
299 * instructions on 32-bit kernels. in emulate_load_store_insn()
301 if (user && !access_ok(addr, 4)) in emulate_load_store_insn()
304 LoadWU(addr, value, res); in emulate_load_store_insn()
308 regs->regs[insn.i_format.rt] = value; in emulate_load_store_insn()
312 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_insn()
318 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_insn()
319 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_insn()
320 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_insn()
321 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_insn()
322 * instructions on 32-bit kernels. in emulate_load_store_insn()
324 if (user && !access_ok(addr, 8)) in emulate_load_store_insn()
327 LoadDW(addr, value, res); in emulate_load_store_insn()
331 regs->regs[insn.i_format.rt] = value; in emulate_load_store_insn()
335 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_insn()
339 if (user && !access_ok(addr, 2)) in emulate_load_store_insn()
343 value = regs->regs[insn.i_format.rt]; in emulate_load_store_insn()
346 StoreHWE(addr, value, res); in emulate_load_store_insn()
348 StoreHW(addr, value, res); in emulate_load_store_insn()
355 if (user && !access_ok(addr, 4)) in emulate_load_store_insn()
359 value = regs->regs[insn.i_format.rt]; in emulate_load_store_insn()
362 StoreWE(addr, value, res); in emulate_load_store_insn()
364 StoreW(addr, value, res); in emulate_load_store_insn()
373 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_insn()
374 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_insn()
375 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_insn()
376 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_insn()
377 * instructions on 32-bit kernels. in emulate_load_store_insn()
379 if (user && !access_ok(addr, 8)) in emulate_load_store_insn()
383 value = regs->regs[insn.i_format.rt]; in emulate_load_store_insn()
384 StoreDW(addr, value, res); in emulate_load_store_insn()
390 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_insn()
405 res = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, in emulate_load_store_insn()
437 fpr = ¤t->thread.fpu.fpr[wd]; in emulate_load_store_insn()
441 if (!access_ok(addr, sizeof(*fpr))) in emulate_load_store_insn()
456 res = __copy_from_user_inatomic(fpr, addr, in emulate_load_store_insn()
477 if (!access_ok(addr, sizeof(*fpr))) in emulate_load_store_insn()
490 res = __copy_to_user_inatomic(addr, fpr, sizeof(*fpr)); in emulate_load_store_insn()
544 regs->cp0_epc = origpc; in emulate_load_store_insn()
545 regs->regs[31] = orig31; in emulate_load_store_insn()
567 /* Recode table from 16-bit register notation to 32-bit GPR. */
570 /* Recode table from 16-bit STORE register notation to 32-bit GPR. */
574 void __user *addr) in emulate_load_store_microMIPS() argument
579 unsigned int reg = 0, rvar; in emulate_load_store_microMIPS() local
589 origpc = regs->cp0_epc; in emulate_load_store_microMIPS()
590 orig31 = regs->regs[31]; in emulate_load_store_microMIPS()
597 pc16 = (unsigned short __user *)msk_isa16_mode(regs->cp0_epc); in emulate_load_store_microMIPS()
600 contpc = regs->cp0_epc + 2; in emulate_load_store_microMIPS()
607 contpc = regs->cp0_epc + 4; in emulate_load_store_microMIPS()
638 reg = insn.mm_x_format.rd; in emulate_load_store_microMIPS()
647 reg = insn.mm_m_format.rd; in emulate_load_store_microMIPS()
648 if (reg == 31) in emulate_load_store_microMIPS()
651 if (user && !access_ok(addr, 8)) in emulate_load_store_microMIPS()
654 LoadW(addr, value, res); in emulate_load_store_microMIPS()
657 regs->regs[reg] = value; in emulate_load_store_microMIPS()
658 addr += 4; in emulate_load_store_microMIPS()
659 LoadW(addr, value, res); in emulate_load_store_microMIPS()
662 regs->regs[reg + 1] = value; in emulate_load_store_microMIPS()
666 reg = insn.mm_m_format.rd; in emulate_load_store_microMIPS()
667 if (reg == 31) in emulate_load_store_microMIPS()
670 if (user && !access_ok(addr, 8)) in emulate_load_store_microMIPS()
673 value = regs->regs[reg]; in emulate_load_store_microMIPS()
674 StoreW(addr, value, res); in emulate_load_store_microMIPS()
677 addr += 4; in emulate_load_store_microMIPS()
678 value = regs->regs[reg + 1]; in emulate_load_store_microMIPS()
679 StoreW(addr, value, res); in emulate_load_store_microMIPS()
686 reg = insn.mm_m_format.rd; in emulate_load_store_microMIPS()
687 if (reg == 31) in emulate_load_store_microMIPS()
690 if (user && !access_ok(addr, 16)) in emulate_load_store_microMIPS()
693 LoadDW(addr, value, res); in emulate_load_store_microMIPS()
696 regs->regs[reg] = value; in emulate_load_store_microMIPS()
697 addr += 8; in emulate_load_store_microMIPS()
698 LoadDW(addr, value, res); in emulate_load_store_microMIPS()
701 regs->regs[reg + 1] = value; in emulate_load_store_microMIPS()
709 reg = insn.mm_m_format.rd; in emulate_load_store_microMIPS()
710 if (reg == 31) in emulate_load_store_microMIPS()
713 if (user && !access_ok(addr, 16)) in emulate_load_store_microMIPS()
716 value = regs->regs[reg]; in emulate_load_store_microMIPS()
717 StoreDW(addr, value, res); in emulate_load_store_microMIPS()
720 addr += 8; in emulate_load_store_microMIPS()
721 value = regs->regs[reg + 1]; in emulate_load_store_microMIPS()
722 StoreDW(addr, value, res); in emulate_load_store_microMIPS()
731 reg = insn.mm_m_format.rd; in emulate_load_store_microMIPS()
732 rvar = reg & 0xf; in emulate_load_store_microMIPS()
733 if ((rvar > 9) || !reg) in emulate_load_store_microMIPS()
735 if (reg & 0x10) { in emulate_load_store_microMIPS()
736 if (user && !access_ok(addr, 4 * (rvar + 1))) in emulate_load_store_microMIPS()
739 if (user && !access_ok(addr, 4 * rvar)) in emulate_load_store_microMIPS()
744 for (i = 16; rvar; rvar--, i++) { in emulate_load_store_microMIPS()
745 LoadW(addr, value, res); in emulate_load_store_microMIPS()
748 addr += 4; in emulate_load_store_microMIPS()
749 regs->regs[i] = value; in emulate_load_store_microMIPS()
751 if ((reg & 0xf) == 9) { in emulate_load_store_microMIPS()
752 LoadW(addr, value, res); in emulate_load_store_microMIPS()
755 addr += 4; in emulate_load_store_microMIPS()
756 regs->regs[30] = value; in emulate_load_store_microMIPS()
758 if (reg & 0x10) { in emulate_load_store_microMIPS()
759 LoadW(addr, value, res); in emulate_load_store_microMIPS()
762 regs->regs[31] = value; in emulate_load_store_microMIPS()
767 reg = insn.mm_m_format.rd; in emulate_load_store_microMIPS()
768 rvar = reg & 0xf; in emulate_load_store_microMIPS()
769 if ((rvar > 9) || !reg) in emulate_load_store_microMIPS()
771 if (reg & 0x10) { in emulate_load_store_microMIPS()
772 if (user && !access_ok(addr, 4 * (rvar + 1))) in emulate_load_store_microMIPS()
775 if (user && !access_ok(addr, 4 * rvar)) in emulate_load_store_microMIPS()
780 for (i = 16; rvar; rvar--, i++) { in emulate_load_store_microMIPS()
781 value = regs->regs[i]; in emulate_load_store_microMIPS()
782 StoreW(addr, value, res); in emulate_load_store_microMIPS()
785 addr += 4; in emulate_load_store_microMIPS()
787 if ((reg & 0xf) == 9) { in emulate_load_store_microMIPS()
788 value = regs->regs[30]; in emulate_load_store_microMIPS()
789 StoreW(addr, value, res); in emulate_load_store_microMIPS()
792 addr += 4; in emulate_load_store_microMIPS()
794 if (reg & 0x10) { in emulate_load_store_microMIPS()
795 value = regs->regs[31]; in emulate_load_store_microMIPS()
796 StoreW(addr, value, res); in emulate_load_store_microMIPS()
804 reg = insn.mm_m_format.rd; in emulate_load_store_microMIPS()
805 rvar = reg & 0xf; in emulate_load_store_microMIPS()
806 if ((rvar > 9) || !reg) in emulate_load_store_microMIPS()
808 if (reg & 0x10) { in emulate_load_store_microMIPS()
809 if (user && !access_ok(addr, 8 * (rvar + 1))) in emulate_load_store_microMIPS()
812 if (user && !access_ok(addr, 8 * rvar)) in emulate_load_store_microMIPS()
818 for (i = 16; rvar; rvar--, i++) { in emulate_load_store_microMIPS()
819 LoadDW(addr, value, res); in emulate_load_store_microMIPS()
822 addr += 4; in emulate_load_store_microMIPS()
823 regs->regs[i] = value; in emulate_load_store_microMIPS()
825 if ((reg & 0xf) == 9) { in emulate_load_store_microMIPS()
826 LoadDW(addr, value, res); in emulate_load_store_microMIPS()
829 addr += 8; in emulate_load_store_microMIPS()
830 regs->regs[30] = value; in emulate_load_store_microMIPS()
832 if (reg & 0x10) { in emulate_load_store_microMIPS()
833 LoadDW(addr, value, res); in emulate_load_store_microMIPS()
836 regs->regs[31] = value; in emulate_load_store_microMIPS()
845 reg = insn.mm_m_format.rd; in emulate_load_store_microMIPS()
846 rvar = reg & 0xf; in emulate_load_store_microMIPS()
847 if ((rvar > 9) || !reg) in emulate_load_store_microMIPS()
849 if (reg & 0x10) { in emulate_load_store_microMIPS()
850 if (user && !access_ok(addr, 8 * (rvar + 1))) in emulate_load_store_microMIPS()
853 if (user && !access_ok(addr, 8 * rvar)) in emulate_load_store_microMIPS()
859 for (i = 16; rvar; rvar--, i++) { in emulate_load_store_microMIPS()
860 value = regs->regs[i]; in emulate_load_store_microMIPS()
861 StoreDW(addr, value, res); in emulate_load_store_microMIPS()
864 addr += 8; in emulate_load_store_microMIPS()
866 if ((reg & 0xf) == 9) { in emulate_load_store_microMIPS()
867 value = regs->regs[30]; in emulate_load_store_microMIPS()
868 StoreDW(addr, value, res); in emulate_load_store_microMIPS()
871 addr += 8; in emulate_load_store_microMIPS()
873 if (reg & 0x10) { in emulate_load_store_microMIPS()
874 value = regs->regs[31]; in emulate_load_store_microMIPS()
875 StoreDW(addr, value, res); in emulate_load_store_microMIPS()
892 reg = insn.mm_m_format.rd; in emulate_load_store_microMIPS()
919 regs->cp0_epc = origpc; in emulate_load_store_microMIPS()
920 regs->regs[31] = orig31; in emulate_load_store_microMIPS()
926 res = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, in emulate_load_store_microMIPS()
940 reg = insn.mm_i_format.rt; in emulate_load_store_microMIPS()
944 reg = insn.mm_i_format.rt; in emulate_load_store_microMIPS()
948 reg = insn.mm_i_format.rt; in emulate_load_store_microMIPS()
952 reg = insn.mm_i_format.rt; in emulate_load_store_microMIPS()
956 reg = insn.mm_i_format.rt; in emulate_load_store_microMIPS()
960 reg = insn.mm_i_format.rt; in emulate_load_store_microMIPS()
964 reg = insn.mm_i_format.rt; in emulate_load_store_microMIPS()
970 reg = insn.mm16_m_format.rlist; in emulate_load_store_microMIPS()
971 rvar = reg + 1; in emulate_load_store_microMIPS()
972 if (user && !access_ok(addr, 4 * rvar)) in emulate_load_store_microMIPS()
975 for (i = 16; rvar; rvar--, i++) { in emulate_load_store_microMIPS()
976 LoadW(addr, value, res); in emulate_load_store_microMIPS()
979 addr += 4; in emulate_load_store_microMIPS()
980 regs->regs[i] = value; in emulate_load_store_microMIPS()
982 LoadW(addr, value, res); in emulate_load_store_microMIPS()
985 regs->regs[31] = value; in emulate_load_store_microMIPS()
990 reg = insn.mm16_m_format.rlist; in emulate_load_store_microMIPS()
991 rvar = reg + 1; in emulate_load_store_microMIPS()
992 if (user && !access_ok(addr, 4 * rvar)) in emulate_load_store_microMIPS()
995 for (i = 16; rvar; rvar--, i++) { in emulate_load_store_microMIPS()
996 value = regs->regs[i]; in emulate_load_store_microMIPS()
997 StoreW(addr, value, res); in emulate_load_store_microMIPS()
1000 addr += 4; in emulate_load_store_microMIPS()
1002 value = regs->regs[31]; in emulate_load_store_microMIPS()
1003 StoreW(addr, value, res); in emulate_load_store_microMIPS()
1014 reg = reg16to32[insn.mm16_rb_format.rt]; in emulate_load_store_microMIPS()
1018 reg = reg16to32[insn.mm16_rb_format.rt]; in emulate_load_store_microMIPS()
1022 reg = reg16to32st[insn.mm16_rb_format.rt]; in emulate_load_store_microMIPS()
1026 reg = reg16to32st[insn.mm16_rb_format.rt]; in emulate_load_store_microMIPS()
1030 reg = insn.mm16_r5_format.rt; in emulate_load_store_microMIPS()
1034 reg = insn.mm16_r5_format.rt; in emulate_load_store_microMIPS()
1038 reg = reg16to32[insn.mm16_r3_format.rt]; in emulate_load_store_microMIPS()
1046 if (user && !access_ok(addr, 2)) in emulate_load_store_microMIPS()
1049 LoadHW(addr, value, res); in emulate_load_store_microMIPS()
1052 regs->regs[reg] = value; in emulate_load_store_microMIPS()
1056 if (user && !access_ok(addr, 2)) in emulate_load_store_microMIPS()
1059 LoadHWU(addr, value, res); in emulate_load_store_microMIPS()
1062 regs->regs[reg] = value; in emulate_load_store_microMIPS()
1066 if (user && !access_ok(addr, 4)) in emulate_load_store_microMIPS()
1069 LoadW(addr, value, res); in emulate_load_store_microMIPS()
1072 regs->regs[reg] = value; in emulate_load_store_microMIPS()
1078 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_microMIPS()
1079 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_microMIPS()
1080 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_microMIPS()
1081 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_microMIPS()
1082 * instructions on 32-bit kernels. in emulate_load_store_microMIPS()
1084 if (user && !access_ok(addr, 4)) in emulate_load_store_microMIPS()
1087 LoadWU(addr, value, res); in emulate_load_store_microMIPS()
1090 regs->regs[reg] = value; in emulate_load_store_microMIPS()
1094 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_microMIPS()
1100 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_microMIPS()
1101 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_microMIPS()
1102 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_microMIPS()
1103 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_microMIPS()
1104 * instructions on 32-bit kernels. in emulate_load_store_microMIPS()
1106 if (user && !access_ok(addr, 8)) in emulate_load_store_microMIPS()
1109 LoadDW(addr, value, res); in emulate_load_store_microMIPS()
1112 regs->regs[reg] = value; in emulate_load_store_microMIPS()
1116 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_microMIPS()
1120 if (user && !access_ok(addr, 2)) in emulate_load_store_microMIPS()
1123 value = regs->regs[reg]; in emulate_load_store_microMIPS()
1124 StoreHW(addr, value, res); in emulate_load_store_microMIPS()
1130 if (user && !access_ok(addr, 4)) in emulate_load_store_microMIPS()
1133 value = regs->regs[reg]; in emulate_load_store_microMIPS()
1134 StoreW(addr, value, res); in emulate_load_store_microMIPS()
1142 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_microMIPS()
1143 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_microMIPS()
1144 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_microMIPS()
1145 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_microMIPS()
1146 * instructions on 32-bit kernels. in emulate_load_store_microMIPS()
1148 if (user && !access_ok(addr, 8)) in emulate_load_store_microMIPS()
1151 value = regs->regs[reg]; in emulate_load_store_microMIPS()
1152 StoreDW(addr, value, res); in emulate_load_store_microMIPS()
1158 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_microMIPS()
1162 regs->cp0_epc = contpc; /* advance or branch */ in emulate_load_store_microMIPS()
1171 regs->cp0_epc = origpc; in emulate_load_store_microMIPS()
1172 regs->regs[31] = orig31; in emulate_load_store_microMIPS()
1194 static void emulate_load_store_MIPS16e(struct pt_regs *regs, void __user * addr) in emulate_load_store_MIPS16e() argument
1198 int reg; in emulate_load_store_MIPS16e() local
1207 origpc = regs->cp0_epc; in emulate_load_store_MIPS16e()
1208 orig31 = regs->regs[31]; in emulate_load_store_MIPS16e()
1237 reg = reg16to32[mips16inst.ri64.ry]; in emulate_load_store_MIPS16e()
1241 reg = reg16to32[mips16inst.ri64.ry]; in emulate_load_store_MIPS16e()
1245 reg = 29; /* GPRSP */ in emulate_load_store_MIPS16e()
1252 reg = reg16to32[mips16inst.ri.rx]; in emulate_load_store_MIPS16e()
1267 reg = reg16to32[mips16inst.ri.rx]; in emulate_load_store_MIPS16e()
1271 reg = reg16to32[mips16inst.ri.rx]; in emulate_load_store_MIPS16e()
1291 reg = 29; /* GPRSP */ in emulate_load_store_MIPS16e()
1295 reg = reg16to32[mips16inst.rri.ry]; in emulate_load_store_MIPS16e()
1307 if (user && !access_ok(addr, 2)) in emulate_load_store_MIPS16e()
1310 LoadHW(addr, value, res); in emulate_load_store_MIPS16e()
1314 regs->regs[reg] = value; in emulate_load_store_MIPS16e()
1318 if (user && !access_ok(addr, 2)) in emulate_load_store_MIPS16e()
1321 LoadHWU(addr, value, res); in emulate_load_store_MIPS16e()
1325 regs->regs[reg] = value; in emulate_load_store_MIPS16e()
1331 if (user && !access_ok(addr, 4)) in emulate_load_store_MIPS16e()
1334 LoadW(addr, value, res); in emulate_load_store_MIPS16e()
1338 regs->regs[reg] = value; in emulate_load_store_MIPS16e()
1344 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_MIPS16e()
1345 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_MIPS16e()
1346 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_MIPS16e()
1347 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_MIPS16e()
1348 * instructions on 32-bit kernels. in emulate_load_store_MIPS16e()
1350 if (user && !access_ok(addr, 4)) in emulate_load_store_MIPS16e()
1353 LoadWU(addr, value, res); in emulate_load_store_MIPS16e()
1357 regs->regs[reg] = value; in emulate_load_store_MIPS16e()
1361 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_MIPS16e()
1368 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_MIPS16e()
1369 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_MIPS16e()
1370 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_MIPS16e()
1371 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_MIPS16e()
1372 * instructions on 32-bit kernels. in emulate_load_store_MIPS16e()
1374 if (user && !access_ok(addr, 8)) in emulate_load_store_MIPS16e()
1377 LoadDW(addr, value, res); in emulate_load_store_MIPS16e()
1381 regs->regs[reg] = value; in emulate_load_store_MIPS16e()
1385 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_MIPS16e()
1389 if (user && !access_ok(addr, 2)) in emulate_load_store_MIPS16e()
1393 value = regs->regs[reg]; in emulate_load_store_MIPS16e()
1394 StoreHW(addr, value, res); in emulate_load_store_MIPS16e()
1401 case MIPS16e_i8_op: /* actually - MIPS16e_swrasp_func */ in emulate_load_store_MIPS16e()
1402 if (user && !access_ok(addr, 4)) in emulate_load_store_MIPS16e()
1406 value = regs->regs[reg]; in emulate_load_store_MIPS16e()
1407 StoreW(addr, value, res); in emulate_load_store_MIPS16e()
1416 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_MIPS16e()
1417 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_MIPS16e()
1418 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_MIPS16e()
1419 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_MIPS16e()
1420 * instructions on 32-bit kernels. in emulate_load_store_MIPS16e()
1422 if (user && !access_ok(addr, 8)) in emulate_load_store_MIPS16e()
1426 value = regs->regs[reg]; in emulate_load_store_MIPS16e()
1427 StoreDW(addr, value, res); in emulate_load_store_MIPS16e()
1433 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_MIPS16e()
1452 regs->cp0_epc = origpc; in emulate_load_store_MIPS16e()
1453 regs->regs[31] = orig31; in emulate_load_store_MIPS16e()
1482 1, regs, regs->cp0_badvaddr); in do_ade()
1486 if (regs->cp0_badvaddr == regs->cp0_epc) in do_ade()
1502 if (get_isa16_mode(regs->cp0_epc)) { in do_ade()
1505 * 16-bit mode? in do_ade()
1507 if (regs->cp0_badvaddr == msk_isa16_mode(regs->cp0_epc)) in do_ade()
1514 (void __user *)regs->cp0_badvaddr); in do_ade()
1520 (void __user *)regs->cp0_badvaddr); in do_ade()
1531 emulate_load_store_insn(regs, (void __user *)regs->cp0_badvaddr, pc); in do_ade()