20 #include <linux/cpu.h>
39 #include <asm/cpu-features.h>
52 static void bmips_set_reset_vec(int cpu, u32 val);
56 /* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
60 static void bmips43xx_send_ipi_single(int cpu, unsigned int action);
61 static void bmips5000_send_ipi_single(int cpu, unsigned int action);
69 #define CPUNUM(cpu, shift)		(((cpu) + bmips_cpu_offset) << (shift))  argument
70 #define ACTION_CLR_IPI(cpu, ipi)	(0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8))  argument
71 #define ACTION_SET_IPI(cpu, ipi)	(0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8))  argument
72 #define ACTION_BOOT_THREAD(cpu)		(0x08 | CPUNUM(cpu, 0))  argument
76 	int i, cpu = 1, boot_cpu = 0;  in bmips_smp_setup()  local
143 				__cpu_number_map[i] = cpu;  in bmips_smp_setup()
144 				__cpu_logical_map[cpu] = i;  in bmips_smp_setup()
145 				cpu++;  in bmips_smp_setup()
159  * IPI IRQ setup - runs on CPU0
186  * Tell the hardware to boot CPUx - runs on CPU0
188 static int bmips_boot_secondary(int cpu, struct task_struct *idle)  in bmips_boot_secondary()  argument
195 	 * Initial boot sequence for secondary CPU:  in bmips_boot_secondary()
196 	 *   bmips_reset_nmi_vec @ a000_0000 ->  in bmips_boot_secondary()
197 	 *   bmips_smp_entry ->  in bmips_boot_secondary()
198 	 *   plat_wired_tlb_setup (cached function call; optional) ->  in bmips_boot_secondary()
202 	 *   play_dead WAIT loop ->  in bmips_boot_secondary()
203 	 *   bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC ->  in bmips_boot_secondary()
204 	 *   eret to play_dead ->  in bmips_boot_secondary()
205 	 *   bmips_secondary_reentry ->  in bmips_boot_secondary()
209 	pr_info("SMP: Booting CPU%d...\n", cpu);  in bmips_boot_secondary()
211 	if (cpumask_test_cpu(cpu, &bmips_booted_mask)) {  in bmips_boot_secondary()
212 		/* kseg1 might not exist if this CPU enabled XKS01 */  in bmips_boot_secondary()
213 		bmips_set_reset_vec(cpu, RESET_FROM_KSEG0);  in bmips_boot_secondary()
218 			bmips43xx_send_ipi_single(cpu, 0);  in bmips_boot_secondary()
221 			bmips5000_send_ipi_single(cpu, 0);  in bmips_boot_secondary()
225 		bmips_set_reset_vec(cpu, RESET_FROM_KSEG1);  in bmips_boot_secondary()
231 			if (cpu_logical_map(cpu) == 1)  in bmips_boot_secondary()
235 			write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));  in bmips_boot_secondary()
238 		cpumask_set_cpu(cpu, &bmips_booted_mask);  in bmips_boot_secondary()
245  * Early setup - runs on secondary CPU after cache probe
264  * Late setup - runs on secondary CPU before entering the idle loop
268 	pr_info("SMP: CPU%d is running\n", smp_processor_id());  in bmips_smp_finish()
281  * Each CPU has two inbound SW IRQs which are independent of all other CPUs.
286 static void bmips5000_send_ipi_single(int cpu, unsigned int action)  in bmips5000_send_ipi_single()  argument
288 	write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION));  in bmips5000_send_ipi_single()
293 	int action = irq - IPI0_IRQ;  in bmips5000_ipi_interrupt()
317  * We use one inbound SW IRQ for each CPU.
327 static void bmips43xx_send_ipi_single(int cpu, unsigned int action)  in bmips43xx_send_ipi_single()  argument
332 	set_c0_cause(cpu ? C_SW1 : C_SW0);  in bmips43xx_send_ipi_single()
333 	per_cpu(ipi_action_mask, cpu) |= action;  in bmips43xx_send_ipi_single()
341 	int action, cpu = irq - IPI0_IRQ;  in bmips43xx_ipi_interrupt()  local
345 	per_cpu(ipi_action_mask, cpu) = 0;  in bmips43xx_ipi_interrupt()
346 	clear_c0_cause(cpu ? C_SW1 : C_SW0);  in bmips43xx_ipi_interrupt()
370 	unsigned int cpu = smp_processor_id();  in bmips_cpu_disable()  local
372 	pr_info("SMP: CPU%d is offline\n", cpu);  in bmips_cpu_disable()
374 	set_cpu_online(cpu, false);  in bmips_cpu_disable()
385 static void bmips_cpu_die(unsigned int cpu)  in bmips_cpu_die()  argument
463 	memcpy((void *)dst, start, end - start);  in bmips_wr_vec()
464 	dma_cache_wback(dst, end - start);  in bmips_wr_vec()
465 	local_flush_icache_range(dst, dst + (end - start));  in bmips_wr_vec()
478 	int cpu;  member
485 	int shift = info->cpu & 0x01 ? 16 : 0;  in bmips_set_reset_vec_remote()
486 	u32 mask = ~(0xffff << shift), val = info->val >> 16;  in bmips_set_reset_vec_remote()
493 		if (info->cpu & 0x02) {  in bmips_set_reset_vec_remote()
505 static void bmips_set_reset_vec(int cpu, u32 val)  in bmips_set_reset_vec()  argument
511 		info.cpu = cpu;  in bmips_set_reset_vec()
517 		if (cpu == 0)  in bmips_set_reset_vec()
544 		 *  - CPU1 will run this from uncached space  in bmips_ebase_setup()
545 		 *  - None of the cacheflush functions are set up yet  in bmips_ebase_setup()
547 		set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0,  in bmips_ebase_setup()
580 	 * Called when starting/restarting a secondary CPU.  in plat_wired_tlb_setup()
644 		"	li	$8, 0x5a455048\n"  in bmips_cpu_setup()
646 		"	.word	0x4008b008\n"	/* mfc0	t0, $22, 8 */  in bmips_cpu_setup()
648 		"	or	$8, $8, $9\n"  in bmips_cpu_setup()
649 		"	.word	0x4088b008\n"	/* mtc0	t0, $22, 8 */  in bmips_cpu_setup()
651 		"	li	$8, 0x0\n"  in bmips_cpu_setup()
654 		: : : "$8", "$9");  in bmips_cpu_setup()
661 		"	li	$8, 0x5a455048\n"  in bmips_cpu_setup()
662 		"	.word	0x4088b00f\n"	/* mtc0 $8, $22, 15 */  in bmips_cpu_setup()
664 		"	.word	0x4008b008\n"	/* mfc0 $8, $22, 8 */  in bmips_cpu_setup()
666 		"	or	$8, $9\n"  in bmips_cpu_setup()
667 		"	.word	0x4088b008\n"	/* mtc0 $8, $22, 8 */  in bmips_cpu_setup()
668 		: : : "$8", "$9");  in bmips_cpu_setup()