Lines Matching +full:reset +full:- +full:assert +full:- +full:ms
1 /* SPDX-License-Identifier: GPL-2.0 */
50 u8 fill0[0x151 - 0x142 - 1];
56 u8 fill1[0x159 - 0x153 - 1];
62 u8 fill2[0x16a - 0x15b - 1];
67 u8 fill3[0x170 - 0x16b - 1];
153 u32 pad1[(0x20000 - 0x00154) / 4];
157 u32 pad2[(0x40000 - 0x20180) / 4];
160 u32 ssram[(0x80000 - 0x40000) / 4];
163 0x80000 - Access to the generic devices selected with DEV0
165 0xA0000 - Access to the generic devices selected with DEV1
167 0xC0000 - Access to the generic devices selected with DEV2
169 0xE0000 - Access to the generic devices selected with DEV3
242 /* ------------------------------------------------------------------------- */
281 #define KM_CSR_M_DATA 0x00000100 /* state of ms data line */
282 #define KM_CSR_M_CLK 0x00000200 /* state of ms clock line */
283 #define KM_CSR_M_PULL_DATA 0x00000400 /* pull ms data line low */
284 #define KM_CSR_M_PULL_CLK 0x00000800 /* pull ms clock line low */
292 SIO_IR to assert */
294 SIO_IR to assert */
347 #define SSCR_RX_RING_DCD 0x00040000 /* post RX record on delta-DCD */
348 #define SSCR_RX_RING_CTS 0x00080000 /* post RX record on delta-CTS */
355 #define SSCR_RESET 0x80000000 /* reset DMA channels */
405 #define SIO_IR_SA_INT 0x00000040 /* port A pass-thru intr */
417 #define SIO_IR_PP_INT 0x00040000 /* P port pass-thru intr */
442 #define SIO_CR_SIO_RESET 0x00000001 /* reset the SIO */
455 #define SIO_CR_ARB_DIAG_IDLE 0x00400000 /* 0 -> active request (ro) */
473 100 / INT_OUT_NS_PER_TICK - 1)
490 #define GPCR_DIR_PHY_RST 0x00000020 /* ethernet PHY reset enable */
493 #define GPCR_PHY_RESET 0x20 /* pin is output to PHY reset */
497 #define GPPR_PHY_RESET_PIN 5 /* GIO pin cntrlling phy reset */
593 /* subsystem IDs supplied by card detection in pci-xtalk-bridge */