Lines Matching full:1
31 #define CVMX_PESCX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000018ull) + ((block_id) & 1)…
32 #define CVMX_PESCX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000418ull) + ((block_id) & 1…
33 #define CVMX_PESCX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000030ull) + ((block_id) & 1) * 0x…
34 #define CVMX_PESCX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000028ull) + ((block_id) & 1) * 0x…
35 …_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000098ull) + ((block_id) & 1) * 0x8000000ull)
36 #define CVMX_PESCX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000000ull) + ((block_id) & 1) …
37 #define CVMX_PESCX_CTL_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000400ull) + ((block_id) & 1)…
38 #define CVMX_PESCX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000008ull) + ((block_id) & 1) * …
39 #define CVMX_PESCX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C80000A0ull) + ((block_id) & 1)…
40 #define CVMX_PESCX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000020ull) + ((block_id) & 1)…
41 …P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000080ull) + ((block_id) & 1) * 0x8000000ull)
42 …P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000088ull) + ((block_id) & 1) * 0x8000000ull)
43 …P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000090ull) + ((block_id) & 1) * 0x8000000ull)
44 …) (CVMX_ADD_IO_SEG(0x00011800C8000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16)
45 …) (CVMX_ADD_IO_SEG(0x00011800C8000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16)
46 #define CVMX_PESCX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000038ull) + ((block_id) & 1)…
53 uint64_t rqdata5:1;
54 uint64_t ctlp_or:1;
55 uint64_t ntlp_or:1;
56 uint64_t ptlp_or:1;
57 uint64_t retry:1;
58 uint64_t rqdata0:1;
59 uint64_t rqdata1:1;
60 uint64_t rqdata2:1;
61 uint64_t rqdata3:1;
62 uint64_t rqdata4:1;
63 uint64_t rqhdr1:1;
64 uint64_t rqhdr0:1;
65 uint64_t sot:1;
67 uint64_t sot:1;
68 uint64_t rqhdr0:1;
69 uint64_t rqhdr1:1;
70 uint64_t rqdata4:1;
71 uint64_t rqdata3:1;
72 uint64_t rqdata2:1;
73 uint64_t rqdata1:1;
74 uint64_t rqdata0:1;
75 uint64_t retry:1;
76 uint64_t ptlp_or:1;
77 uint64_t ntlp_or:1;
78 uint64_t ctlp_or:1;
79 uint64_t rqdata5:1;
86 uint64_t ctlp_or:1;
87 uint64_t ntlp_or:1;
88 uint64_t ptlp_or:1;
89 uint64_t retry:1;
90 uint64_t rqdata0:1;
91 uint64_t rqdata1:1;
92 uint64_t rqdata2:1;
93 uint64_t rqdata3:1;
94 uint64_t rqdata4:1;
95 uint64_t rqhdr1:1;
96 uint64_t rqhdr0:1;
97 uint64_t sot:1;
99 uint64_t sot:1;
100 uint64_t rqhdr0:1;
101 uint64_t rqhdr1:1;
102 uint64_t rqdata4:1;
103 uint64_t rqdata3:1;
104 uint64_t rqdata2:1;
105 uint64_t rqdata1:1;
106 uint64_t rqdata0:1;
107 uint64_t retry:1;
108 uint64_t ptlp_or:1;
109 uint64_t ntlp_or:1;
110 uint64_t ctlp_or:1;
121 uint64_t cto_p2e:1;
122 uint64_t e2p_cpl:1;
123 uint64_t e2p_n:1;
124 uint64_t e2p_p:1;
125 uint64_t e2p_rsl:1;
126 uint64_t dbg_p2e:1;
127 uint64_t peai_p2e:1;
128 uint64_t rsl_p2e:1;
129 uint64_t pef_tpf1:1;
130 uint64_t pef_tpf0:1;
131 uint64_t pef_tnf:1;
132 uint64_t pef_tcf1:1;
133 uint64_t pef_tc0:1;
134 uint64_t ppf:1;
136 uint64_t ppf:1;
137 uint64_t pef_tc0:1;
138 uint64_t pef_tcf1:1;
139 uint64_t pef_tnf:1;
140 uint64_t pef_tpf0:1;
141 uint64_t pef_tpf1:1;
142 uint64_t rsl_p2e:1;
143 uint64_t peai_p2e:1;
144 uint64_t dbg_p2e:1;
145 uint64_t e2p_rsl:1;
146 uint64_t e2p_p:1;
147 uint64_t e2p_n:1;
148 uint64_t e2p_cpl:1;
149 uint64_t cto_p2e:1;
202 uint64_t lane_swp:1;
203 uint64_t pm_xtoff:1;
204 uint64_t pm_xpme:1;
205 uint64_t ob_p_cmd:1;
207 uint64_t nf_ecrc:1;
208 uint64_t dly_one:1;
209 uint64_t lnk_enb:1;
210 uint64_t ro_ctlp:1;
211 uint64_t reserved_2_2:1;
212 uint64_t inv_ecrc:1;
213 uint64_t inv_lcrc:1;
215 uint64_t inv_lcrc:1;
216 uint64_t inv_ecrc:1;
217 uint64_t reserved_2_2:1;
218 uint64_t ro_ctlp:1;
219 uint64_t lnk_enb:1;
220 uint64_t dly_one:1;
221 uint64_t nf_ecrc:1;
223 uint64_t ob_p_cmd:1;
224 uint64_t pm_xpme:1;
225 uint64_t pm_xtoff:1;
226 uint64_t lane_swp:1;
239 uint64_t reserved_12_12:1;
240 uint64_t pm_xtoff:1;
241 uint64_t pm_xpme:1;
242 uint64_t ob_p_cmd:1;
244 uint64_t nf_ecrc:1;
245 uint64_t dly_one:1;
246 uint64_t lnk_enb:1;
247 uint64_t ro_ctlp:1;
248 uint64_t reserved_2_2:1;
249 uint64_t inv_ecrc:1;
250 uint64_t inv_lcrc:1;
252 uint64_t inv_lcrc:1;
253 uint64_t inv_ecrc:1;
254 uint64_t reserved_2_2:1;
255 uint64_t ro_ctlp:1;
256 uint64_t lnk_enb:1;
257 uint64_t dly_one:1;
258 uint64_t nf_ecrc:1;
260 uint64_t ob_p_cmd:1;
261 uint64_t pm_xpme:1;
262 uint64_t pm_xtoff:1;
263 uint64_t reserved_12_12:1;
277 uint64_t pclk_run:1;
278 uint64_t pcierst:1;
280 uint64_t pcierst:1;
281 uint64_t pclk_run:1;
288 uint64_t pcierst:1;
290 uint64_t pcierst:1;
301 uint64_t ecrc_e:1;
302 uint64_t rawwpp:1;
303 uint64_t racpp:1;
304 uint64_t ramtlp:1;
305 uint64_t rarwdns:1;
306 uint64_t caar:1;
307 uint64_t racca:1;
308 uint64_t racur:1;
309 uint64_t rauc:1;
310 uint64_t rqo:1;
311 uint64_t fcuv:1;
312 uint64_t rpe:1;
313 uint64_t fcpvwt:1;
314 uint64_t dpeoosd:1;
315 uint64_t rtwdle:1;
316 uint64_t rdwdle:1;
317 uint64_t mre:1;
318 uint64_t rte:1;
319 uint64_t acto:1;
320 uint64_t rvdm:1;
321 uint64_t rumep:1;
322 uint64_t rptamrc:1;
323 uint64_t rpmerc:1;
324 uint64_t rfemrc:1;
325 uint64_t rnfemrc:1;
326 uint64_t rcemrc:1;
327 uint64_t rpoison:1;
328 uint64_t recrce:1;
329 uint64_t rtlplle:1;
330 uint64_t rtlpmal:1;
331 uint64_t spoison:1;
333 uint64_t spoison:1;
334 uint64_t rtlpmal:1;
335 uint64_t rtlplle:1;
336 uint64_t recrce:1;
337 uint64_t rpoison:1;
338 uint64_t rcemrc:1;
339 uint64_t rnfemrc:1;
340 uint64_t rfemrc:1;
341 uint64_t rpmerc:1;
342 uint64_t rptamrc:1;
343 uint64_t rumep:1;
344 uint64_t rvdm:1;
345 uint64_t acto:1;
346 uint64_t rte:1;
347 uint64_t mre:1;
348 uint64_t rdwdle:1;
349 uint64_t rtwdle:1;
350 uint64_t dpeoosd:1;
351 uint64_t fcpvwt:1;
352 uint64_t rpe:1;
353 uint64_t fcuv:1;
354 uint64_t rqo:1;
355 uint64_t rauc:1;
356 uint64_t racur:1;
357 uint64_t racca:1;
358 uint64_t caar:1;
359 uint64_t rarwdns:1;
360 uint64_t ramtlp:1;
361 uint64_t racpp:1;
362 uint64_t rawwpp:1;
363 uint64_t ecrc_e:1;
374 uint64_t ecrc_e:1;
375 uint64_t rawwpp:1;
376 uint64_t racpp:1;
377 uint64_t ramtlp:1;
378 uint64_t rarwdns:1;
379 uint64_t caar:1;
380 uint64_t racca:1;
381 uint64_t racur:1;
382 uint64_t rauc:1;
383 uint64_t rqo:1;
384 uint64_t fcuv:1;
385 uint64_t rpe:1;
386 uint64_t fcpvwt:1;
387 uint64_t dpeoosd:1;
388 uint64_t rtwdle:1;
389 uint64_t rdwdle:1;
390 uint64_t mre:1;
391 uint64_t rte:1;
392 uint64_t acto:1;
393 uint64_t rvdm:1;
394 uint64_t rumep:1;
395 uint64_t rptamrc:1;
396 uint64_t rpmerc:1;
397 uint64_t rfemrc:1;
398 uint64_t rnfemrc:1;
399 uint64_t rcemrc:1;
400 uint64_t rpoison:1;
401 uint64_t recrce:1;
402 uint64_t rtlplle:1;
403 uint64_t rtlpmal:1;
404 uint64_t spoison:1;
406 uint64_t spoison:1;
407 uint64_t rtlpmal:1;
408 uint64_t rtlplle:1;
409 uint64_t recrce:1;
410 uint64_t rpoison:1;
411 uint64_t rcemrc:1;
412 uint64_t rnfemrc:1;
413 uint64_t rfemrc:1;
414 uint64_t rpmerc:1;
415 uint64_t rptamrc:1;
416 uint64_t rumep:1;
417 uint64_t rvdm:1;
418 uint64_t acto:1;
419 uint64_t rte:1;
420 uint64_t mre:1;
421 uint64_t rdwdle:1;
422 uint64_t rtwdle:1;
423 uint64_t dpeoosd:1;
424 uint64_t fcpvwt:1;
425 uint64_t rpe:1;
426 uint64_t fcuv:1;
427 uint64_t rqo:1;
428 uint64_t rauc:1;
429 uint64_t racur:1;
430 uint64_t racca:1;
431 uint64_t caar:1;
432 uint64_t rarwdns:1;
433 uint64_t ramtlp:1;
434 uint64_t racpp:1;
435 uint64_t rawwpp:1;
436 uint64_t ecrc_e:1;
447 uint64_t pm_dst:1;
448 uint64_t pm_stat:1;
449 uint64_t pm_en:1;
450 uint64_t aux_en:1;
452 uint64_t aux_en:1;
453 uint64_t pm_en:1;
454 uint64_t pm_stat:1;
455 uint64_t pm_dst:1;