4  * Copyright (C) 2010-2017 Cavium Networks
28 	/* Reference clock select for SuperSpeed and HighSpeed PLLs:
29 	 *	0x0 = Both PLLs use DLMC_REF_CLK0 for reference clock
30 	 *	0x1 = Both PLLs use DLMC_REF_CLK1 for reference clock
31 	 *	0x2 = SuperSpeed PLL uses DLMC_REF_CLK0 for reference clock &
32 	 *	      HighSpeed PLL uses PLL_REF_CLK for reference clck
33 	 *	0x3 = SuperSpeed PLL uses DLMC_REF_CLK1 for reference clock &
34 	 *	      HighSpeed PLL uses PLL_REF_CLK for reference clck
37 	/* 1 = Spread-spectrum clock enable, 0 = SS clock disable */
39 	/* Spread-spectrum clock modulation range:
40 	 *	0x0 = -4980 ppm downspread
41 	 *	0x1 = -4492 ppm downspread
42 	 *	0x2 = -4003 ppm downspread
43 	 *	0x3 - 0x7 = Reserved
46 	/* Enable non-standard oscillator frequencies:
47 	 *	[55:53] = modules -1
51 	/* Reference clock multiplier for non-standard frequencies:
58 	/* Enable reference clock to prescaler for SuperSpeed functionality.
62 	/* Divide the reference clock by 2 before entering the
70 	/* Select reference clock freqnuency for both PLL blocks:
79 	/* Select bypass input to controller clock divider:
88 	/* Clock divider select:
151 	/* Bus-master enable: 0x0 = Disabled (stall DMAs), 0x1 = enabled */
156 	 *	0x0 = Overcurrent indication from off-chip is active-low
157 	 *	0x1 = Overcurrent indication from off-chip is active-high
163 	 *	0x0 = Port power to off-chip is active-low
164 	 *	0x1 = Port power to off-chip is active-high
177 	/* Out-of-bound UAHC register access: 0 = read, 1 = write */
181 	/* SRCID error log for out-of-bound UAHC register access:
183 	 *	[57] = Request source: 0 = core, 1 = NCB-device
184 	 *	[56:51] = Core/NCB-device number, [56] always 0 for NCB devices
196 	/* Select the IOI read command used by DMA accesses */
200 	/* Select endian format for DMA accesses to the L2c:
209 	/* Select endian format for IOI CSR access to UAHC:
235 	struct device_node *node = dev->of_node;  in dwc3_octeon_config_power()
249 			return -EINVAL;  in dwc3_octeon_config_power()
297 	if (dev->of_node) {  in dwc3_octeon_clocks_start()
301 		i = of_property_read_u32(dev->of_node,  in dwc3_octeon_clocks_start()
302 					 "refclk-frequency", &clock_rate);  in dwc3_octeon_clocks_start()
304 			pr_err("No UCTL \"refclk-frequency\"\n");  in dwc3_octeon_clocks_start()
305 			return -EINVAL;  in dwc3_octeon_clocks_start()
307 		i = of_property_read_string(dev->of_node,  in dwc3_octeon_clocks_start()
308 					    "refclk-type-ss", &ss_clock_type);  in dwc3_octeon_clocks_start()
310 			pr_err("No UCTL \"refclk-type-ss\"\n");  in dwc3_octeon_clocks_start()
311 			return -EINVAL;  in dwc3_octeon_clocks_start()
313 		i = of_property_read_string(dev->of_node,  in dwc3_octeon_clocks_start()
314 					    "refclk-type-hs", &hs_clock_type);  in dwc3_octeon_clocks_start()
316 			pr_err("No UCTL \"refclk-type-hs\"\n");  in dwc3_octeon_clocks_start()
317 			return -EINVAL;  in dwc3_octeon_clocks_start()
348 		return -EINVAL;  in dwc3_octeon_clocks_start()
356 	/* Step 2: Select GPIO for overcurrent indication, if desired. SKIP */  in dwc3_octeon_clocks_start()
370 	/* Step 4b: Select controller clock frequency. */  in dwc3_octeon_clocks_start()
384 			return -EINVAL;  in dwc3_octeon_clocks_start()
392 	/* Step 5a: Reference clock configuration. */  in dwc3_octeon_clocks_start()
416 	/* Step 5b: Configure and enable spread-spectrum for SuperSpeed. */  in dwc3_octeon_clocks_start()
429 	/* Step 7: Wait 10 controller-clock cycles to take effect. */  in dwc3_octeon_clocks_start()
437 	/* Step 8b: Wait 10 controller-clock cycles. */  in dwc3_octeon_clocks_start()
440 	/* Steo 8c: Setup power-power control. */  in dwc3_octeon_clocks_start()
443 		return -EINVAL;  in dwc3_octeon_clocks_start()
451 	/* Step 8e: Wait 10 controller-clock cycles. */  in dwc3_octeon_clocks_start()
498 	const char compat_node_name[] = "cavium,octeon-7130-usb-uctl";  in dwc3_octeon_device_init()
512 			return -ENODEV;  in dwc3_octeon_device_init()
517 				return -ENODEV;  in dwc3_octeon_device_init()
527 				put_device(&pdev->dev);  in dwc3_octeon_device_init()
532 			dwc3_octeon_clocks_start(&pdev->dev, (u64)base);  in dwc3_octeon_device_init()
535 			dev_info(&pdev->dev, "clocks initialized.\n");  in dwc3_octeon_device_init()
537 			devm_iounmap(&pdev->dev, base);  in dwc3_octeon_device_init()
538 			devm_release_mem_region(&pdev->dev, res->start,  in dwc3_octeon_device_init()