7  * Copyright (c) 2003-2017 Cavium, Inc.
14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29  * Implementation of the Level 2 Cache (L2C) control,
36 #include <asm/octeon/cvmx-l2c.h>
37 #include <asm/octeon/cvmx-spinlock.h>
43  * NOTE: This only protects calls from within a single application -
55 		return -1;  in cvmx_l2c_get_core_way_partition()
89 	valid_mask = (0x1 << cvmx_l2c_get_num_assoc()) - 1;  in cvmx_l2c_set_core_way_partition()
95 		return -1;  in cvmx_l2c_set_core_way_partition()
99 		return -1;  in cvmx_l2c_set_core_way_partition()
146 	valid_mask = (0x1 << cvmx_l2c_get_num_assoc()) - 1;  in cvmx_l2c_set_hw_way_partition()
151 		return -1;  in cvmx_l2c_set_hw_way_partition()
286  * Helper function use to fault in cache lines for L2 cache locking
288  * @addr:   Address of base of memory region to read into L2 cache
296 	 * Adjust addr and length so we get all cache lines even for  in fault_in()
297 	 * small ranges spanning two cache lines.  in fault_in()
303 	 * Invalidate L1 cache to make sure all loads result in data  in fault_in()
309 		len -= CVMX_CACHE_LINE_SIZE;  in fault_in()
339 			return -1;  in cvmx_l2c_lock_line()
345 			return -1;  in cvmx_l2c_lock_line()
380 			int alias_shift = CVMX_L2C_IDX_ADDR_SHIFT + 2 * CVMX_L2_SET_BITS - 1;  in cvmx_l2c_lock_line()
381 			uint64_t addr_tmp = addr ^ (addr & ((1 << alias_shift) - 1)) >> CVMX_L2_SET_BITS;  in cvmx_l2c_lock_line()
418 	/* Round start/end to cache line boundaries */  in cvmx_l2c_lock_mem_region()
426 		len -= CVMX_CACHE_LINE_SIZE;  in cvmx_l2c_lock_mem_region()
469 …tag_addr = ((address >> CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) & ((1 << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) - 1…  in cvmx_l2c_unlock_line()
473 		 * address directly, so finding the cache line used by  in cvmx_l2c_unlock_line()
493 …tag_addr = ((address >> CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) & ((1 << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) - 1…  in cvmx_l2c_unlock_line()
509 	/* Round start/end to cache line boundaries */  in cvmx_l2c_unlock_mem_region()
516 		len -= CVMX_CACHE_LINE_SIZE;  in cvmx_l2c_unlock_mem_region()
531 		__BITFIELD_FIELD(uint64_t D:1,		/* Line dirty */
540 		__BITFIELD_FIELD(uint64_t D:1,		/* Line dirty */
549 		__BITFIELD_FIELD(uint64_t D:1,		/* Line dirty */
558 		__BITFIELD_FIELD(uint64_t D:1,		/* Line dirty */
567 		__BITFIELD_FIELD(uint64_t D:1,		/* Line dirty */
573 	struct cvmx_l2c_tag_cn58xx cn56xx;	/* 2048 sets */
574 	struct cvmx_l2c_tag_cn31xx cn52xx;	/* 512 sets */
638 		"cache 9, 0($0)\n\t"		 /* Invalidate dcache to discard debug data */  in __read_l2_tag()
660 		cvmx_dprintf("ERROR: cvmx_l2c_get_tag index out of range (arg: %d, max: %d)\n",  in cvmx_l2c_get_tag()
670 		 * Use L2 cache Index load tag cache instruction, as  in cvmx_l2c_get_tag()
671 		 * hardware loads the virtual tag for the L2 cache  in cvmx_l2c_get_tag()
680 		tag.s.D	    = l2c_tadx_tag.s.dirty;  in cvmx_l2c_get_tag()
695 			tag.s.D	   = tmp_tag.cn58xx.D;  in cvmx_l2c_get_tag()
701 			tag.s.D	   = tmp_tag.cn38xx.D;  in cvmx_l2c_get_tag()
707 			tag.s.D	   = tmp_tag.cn31xx.D;  in cvmx_l2c_get_tag()
713 			tag.s.D	   = tmp_tag.cn30xx.D;  in cvmx_l2c_get_tag()
719 			tag.s.D	   = tmp_tag.cn50xx.D;  in cvmx_l2c_get_tag()
768  * Return log base 2 of the number of sets in the L2 cache
775 		l2_set_bits = 11;	/* 2048 sets */  in cvmx_l2c_get_set_bits()
777 		l2_set_bits = 10;	/* 1024 sets */  in cvmx_l2c_get_set_bits()
779 		l2_set_bits = 9;	/* 512 sets */  in cvmx_l2c_get_set_bits()
781 		l2_set_bits = 8;	/* 256 sets */  in cvmx_l2c_get_set_bits()
783 		l2_set_bits = 7;	/* 128 sets */  in cvmx_l2c_get_set_bits()
786 		l2_set_bits = 11;	/* 2048 sets */  in cvmx_l2c_get_set_bits()
791 /* Return the number of sets in the L2 Cache */
797 /* Return the number of associations in the L2 Cache */
818 	/* Check to see if part of the cache is disabled */  in cvmx_l2c_get_num_assoc()
830 		 * 0 0 16-way 2MB cache  in cvmx_l2c_get_num_assoc()
831 		 * 0 1 12-way 1.5MB cache  in cvmx_l2c_get_num_assoc()
832 		 * 1 0 8-way 1MB cache  in cvmx_l2c_get_num_assoc()
833 		 * 1 1 4-way 512KB cache  in cvmx_l2c_get_num_assoc()
860  * Flush a line from the L2 cache
862  * sets the core to the 'debug' core in order to flush the line.
884 		 * Bits<20:17> select the way of the cache block involved in  in cvmx_l2c_flush_line()