Lines Matching +full:bus +full:- +full:range
1 // SPDX-License-Identifier: GPL-2.0-or-later
12 * Common pmac/prep/chrp pci routines. -- Cort
35 #include <asm/pci-bridge.h>
60 phb->global_number = global_phb_number++; in pcibios_alloc_controller()
61 list_add_tail(&phb->list_node, &hose_list); in pcibios_alloc_controller()
63 phb->dn = dev; in pcibios_alloc_controller()
64 phb->is_dynamic = mem_init_done; in pcibios_alloc_controller()
71 list_del(&phb->list_node); in pcibios_free_controller()
74 if (phb->is_dynamic) in pcibios_free_controller()
80 return resource_size(&hose->io_resource); in pcibios_io_size()
92 if (address >= hose->io_base_virt && in pcibios_vaddr_is_ioport()
93 address < (hose->io_base_virt + size)) { in pcibios_vaddr_is_ioport()
111 if (address >= hose->io_base_phys && in pci_address_to_pio()
112 address < (hose->io_base_phys + size)) { in pci_address_to_pio()
114 (unsigned long)hose->io_base_virt - _IO_BASE; in pci_address_to_pio()
115 ret = base + (address - hose->io_base_phys); in pci_address_to_pio()
126 * PCI bus numbers have not yet been assigned, and you need to
137 if (hose->dn == node) in pci_find_hose_for_OF_device()
139 node = node->parent; in pci_find_hose_for_OF_device()
146 /* No special bus mastering setup handling */ in pcibios_set_master()
150 * Platform support for /proc/bus/pci/X/Y mmap()s.
155 struct pci_controller *hose = pci_bus_to_host(pdev->bus); in pci_iobar_pfn()
159 return -EINVAL; /* should never happen */ in pci_iobar_pfn()
162 ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE; in pci_iobar_pfn()
164 vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT; in pci_iobar_pfn()
189 struct resource *rp = &pdev->resource[i]; in pci_phys_mem_access_prot()
190 int flags = rp->flags; in pci_phys_mem_access_prot()
195 /* In the range of this resource? */ in pci_phys_mem_access_prot()
196 if (offset < (rp->start & PAGE_MASK) || in pci_phys_mem_access_prot()
197 offset > rp->end) in pci_phys_mem_access_prot()
206 if (found->flags & IORESOURCE_PREFETCH) in pci_phys_mem_access_prot()
211 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n", in pci_phys_mem_access_prot()
217 /* This provides legacy IO read access on a bus */
218 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size) in pci_legacy_read() argument
221 struct pci_controller *hose = pci_bus_to_host(bus); in pci_legacy_read()
222 struct resource *rp = &hose->io_resource; in pci_legacy_read()
225 /* Check if port can be supported by that bus. We only check in pci_legacy_read()
226 * the ranges of the PHB though, not the bus itself as the rules in pci_legacy_read()
230 offset = (unsigned long)hose->io_base_virt - _IO_BASE; in pci_legacy_read()
233 if (!(rp->flags & IORESOURCE_IO)) in pci_legacy_read()
234 return -ENXIO; in pci_legacy_read()
235 if (offset < rp->start || (offset + size) > rp->end) in pci_legacy_read()
236 return -ENXIO; in pci_legacy_read()
237 addr = hose->io_base_virt + port; in pci_legacy_read()
245 return -EINVAL; in pci_legacy_read()
250 return -EINVAL; in pci_legacy_read()
254 return -EINVAL; in pci_legacy_read()
257 /* This provides legacy IO write access on a bus */
258 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size) in pci_legacy_write() argument
261 struct pci_controller *hose = pci_bus_to_host(bus); in pci_legacy_write()
262 struct resource *rp = &hose->io_resource; in pci_legacy_write()
265 /* Check if port can be supported by that bus. We only check in pci_legacy_write()
266 * the ranges of the PHB though, not the bus itself as the rules in pci_legacy_write()
270 offset = (unsigned long)hose->io_base_virt - _IO_BASE; in pci_legacy_write()
273 if (!(rp->flags & IORESOURCE_IO)) in pci_legacy_write()
274 return -ENXIO; in pci_legacy_write()
275 if (offset < rp->start || (offset + size) > rp->end) in pci_legacy_write()
276 return -ENXIO; in pci_legacy_write()
277 addr = hose->io_base_virt + port; in pci_legacy_write()
290 return -EINVAL; in pci_legacy_write()
295 return -EINVAL; in pci_legacy_write()
299 return -EINVAL; in pci_legacy_write()
302 /* This provides legacy IO or memory mmap access on a bus */
303 int pci_mmap_legacy_page_range(struct pci_bus *bus, in pci_mmap_legacy_page_range() argument
307 struct pci_controller *hose = pci_bus_to_host(bus); in pci_mmap_legacy_page_range()
309 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; in pci_mmap_legacy_page_range()
310 resource_size_t size = vma->vm_end - vma->vm_start; in pci_mmap_legacy_page_range()
314 pci_domain_nr(bus), bus->number, in pci_mmap_legacy_page_range()
317 (unsigned long long)(offset + size - 1)); in pci_mmap_legacy_page_range()
327 if ((offset + size) > hose->isa_mem_size) { in pci_mmap_legacy_page_range()
328 pr_debug("Process %s (pid:%d) mapped non-existing PCI", in pci_mmap_legacy_page_range()
329 current->comm, current->pid); in pci_mmap_legacy_page_range()
331 pci_domain_nr(bus), bus->number); in pci_mmap_legacy_page_range()
332 if (vma->vm_flags & VM_SHARED) in pci_mmap_legacy_page_range()
336 offset += hose->isa_mem_phys; in pci_mmap_legacy_page_range()
338 unsigned long io_offset = (unsigned long)hose->io_base_virt - in pci_mmap_legacy_page_range()
341 rp = &hose->io_resource; in pci_mmap_legacy_page_range()
342 if (!(rp->flags & IORESOURCE_IO)) in pci_mmap_legacy_page_range()
343 return -ENXIO; in pci_mmap_legacy_page_range()
344 if (roffset < rp->start || (roffset + size) > rp->end) in pci_mmap_legacy_page_range()
345 return -ENXIO; in pci_mmap_legacy_page_range()
346 offset += hose->io_base_phys; in pci_mmap_legacy_page_range()
348 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset); in pci_mmap_legacy_page_range()
350 vma->vm_pgoff = offset >> PAGE_SHIFT; in pci_mmap_legacy_page_range()
351 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); in pci_mmap_legacy_page_range()
352 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, in pci_mmap_legacy_page_range()
353 vma->vm_end - vma->vm_start, in pci_mmap_legacy_page_range()
354 vma->vm_page_prot); in pci_mmap_legacy_page_range()
363 if (rsrc->flags & IORESOURCE_IO) { in pci_resource_to_user()
364 pcibios_resource_to_bus(dev->bus, ®ion, in pci_resource_to_user()
375 * That means we may have 64-bit values where some apps only expect in pci_resource_to_user()
376 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO). in pci_resource_to_user()
378 *start = rsrc->start; in pci_resource_to_user()
379 *end = rsrc->end; in pci_resource_to_user()
383 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
386 * @primary: set if primary bus (32 bits only, soon to be deprecated)
395 * - We can only cope with one IO space range and up to 3 Memory space
399 * - We can only cope with all memory ranges having the same offset
408 * - Some busses have IO space not starting at 0, which causes trouble with
412 * - Some 32 bits platforms such as 4xx can have physical space larger than
418 int memno = 0, isa_hole = -1; in pci_process_bridge_OF_ranges()
421 struct of_pci_range range; in pci_process_bridge_OF_ranges() local
432 for_each_of_pci_range(&parser, &range) { in pci_process_bridge_OF_ranges()
435 /* If we failed translation or got a zero-sized region in pci_process_bridge_OF_ranges()
440 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0) in pci_process_bridge_OF_ranges()
445 switch (range.flags & IORESOURCE_TYPE_BITS) { in pci_process_bridge_OF_ranges()
447 pr_info(" IO 0x%016llx..0x%016llx -> 0x%016llx\n", in pci_process_bridge_OF_ranges()
448 range.cpu_addr, range.cpu_addr + range.size - 1, in pci_process_bridge_OF_ranges()
449 range.pci_addr); in pci_process_bridge_OF_ranges()
451 /* We support only one IO range */ in pci_process_bridge_OF_ranges()
452 if (hose->pci_io_size) { in pci_process_bridge_OF_ranges()
453 pr_info(" \\--> Skipped (too many) !\n"); in pci_process_bridge_OF_ranges()
457 if (range.size > 0x01000000) in pci_process_bridge_OF_ranges()
458 range.size = 0x01000000; in pci_process_bridge_OF_ranges()
461 hose->io_base_virt = ioremap(range.cpu_addr, in pci_process_bridge_OF_ranges()
462 range.size); in pci_process_bridge_OF_ranges()
467 (unsigned long)hose->io_base_virt; in pci_process_bridge_OF_ranges()
471 hose->pci_io_size = range.pci_addr + range.size; in pci_process_bridge_OF_ranges()
472 hose->io_base_phys = range.cpu_addr - range.pci_addr; in pci_process_bridge_OF_ranges()
475 res = &hose->io_resource; in pci_process_bridge_OF_ranges()
476 range.cpu_addr = range.pci_addr; in pci_process_bridge_OF_ranges()
480 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", in pci_process_bridge_OF_ranges()
481 range.cpu_addr, range.cpu_addr + range.size - 1, in pci_process_bridge_OF_ranges()
482 range.pci_addr, in pci_process_bridge_OF_ranges()
483 (range.flags & IORESOURCE_PREFETCH) ? in pci_process_bridge_OF_ranges()
488 pr_info(" \\--> Skipped (too many) !\n"); in pci_process_bridge_OF_ranges()
492 if (range.pci_addr == 0) { in pci_process_bridge_OF_ranges()
493 isa_mb = range.cpu_addr; in pci_process_bridge_OF_ranges()
496 isa_mem_base = range.cpu_addr; in pci_process_bridge_OF_ranges()
497 hose->isa_mem_phys = range.cpu_addr; in pci_process_bridge_OF_ranges()
498 hose->isa_mem_size = range.size; in pci_process_bridge_OF_ranges()
501 /* We get the PCI/Mem offset from the first range or in pci_process_bridge_OF_ranges()
506 (isa_hole >= 0 && range.pci_addr != 0 && in pci_process_bridge_OF_ranges()
507 hose->pci_mem_offset == isa_mb)) in pci_process_bridge_OF_ranges()
508 hose->pci_mem_offset = range.cpu_addr - in pci_process_bridge_OF_ranges()
509 range.pci_addr; in pci_process_bridge_OF_ranges()
510 else if (range.pci_addr != 0 && in pci_process_bridge_OF_ranges()
511 hose->pci_mem_offset != range.cpu_addr - in pci_process_bridge_OF_ranges()
512 range.pci_addr) { in pci_process_bridge_OF_ranges()
513 pr_info(" \\--> Skipped (offset mismatch) !\n"); in pci_process_bridge_OF_ranges()
518 res = &hose->mem_resources[memno++]; in pci_process_bridge_OF_ranges()
522 res->name = dev->full_name; in pci_process_bridge_OF_ranges()
523 res->flags = range.flags; in pci_process_bridge_OF_ranges()
524 res->start = range.cpu_addr; in pci_process_bridge_OF_ranges()
525 res->end = range.cpu_addr + range.size - 1; in pci_process_bridge_OF_ranges()
526 res->parent = res->child = res->sibling = NULL; in pci_process_bridge_OF_ranges()
530 /* If there's an ISA hole and the pci_mem_offset is -not- matching in pci_process_bridge_OF_ranges()
534 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) { in pci_process_bridge_OF_ranges()
538 memmove(&hose->mem_resources[isa_hole], in pci_process_bridge_OF_ranges()
539 &hose->mem_resources[next], in pci_process_bridge_OF_ranges()
540 sizeof(struct resource) * (memno - next)); in pci_process_bridge_OF_ranges()
541 hose->mem_resources[--memno].flags = 0; in pci_process_bridge_OF_ranges()
546 int pci_proc_domain(struct pci_bus *bus) in pci_proc_domain() argument
548 return pci_domain_nr(bus); in pci_proc_domain()
556 struct pci_controller *hose = pci_bus_to_host(dev->bus); in pcibios_fixup_resources()
565 struct resource *res = dev->resource + i; in pcibios_fixup_resources()
566 if (!res->flags) in pcibios_fixup_resources()
568 if (res->start == 0) { in pcibios_fixup_resources()
569 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]", in pcibios_fixup_resources()
571 (unsigned long long)res->start, in pcibios_fixup_resources()
572 (unsigned long long)res->end, in pcibios_fixup_resources()
573 (unsigned int)res->flags); in pcibios_fixup_resources()
575 res->end -= res->start; in pcibios_fixup_resources()
576 res->start = 0; in pcibios_fixup_resources()
577 res->flags |= IORESOURCE_UNSET; in pcibios_fixup_resources()
581 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n", in pcibios_fixup_resources()
583 (unsigned long long)res->start, in pcibios_fixup_resources()
584 (unsigned long long)res->end, in pcibios_fixup_resources()
585 (unsigned int)res->flags); in pcibios_fixup_resources()
592 dev->irq = of_irq_parse_and_map_pci(dev, 0, 0); in pcibios_add_device()
608 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { in reparent_resources()
609 if (p->end < res->start) in reparent_resources()
611 if (res->end < p->start) in reparent_resources()
613 if (p->start < res->start || p->end > res->end) in reparent_resources()
614 return -1; /* not completely contained */ in reparent_resources()
619 return -1; /* didn't find any conflicting entries? */ in reparent_resources()
620 res->parent = parent; in reparent_resources()
621 res->child = *firstpp; in reparent_resources()
622 res->sibling = *pp; in reparent_resources()
625 for (p = res->child; p != NULL; p = p->sibling) { in reparent_resources()
626 p->parent = res; in reparent_resources()
628 p->name, in reparent_resources()
629 (unsigned long long)p->start, in reparent_resources()
630 (unsigned long long)p->end, res->name); in reparent_resources()
638 * On the other hand, we cannot just re-allocate all devices, as it would
644 * - I/O or memory regions not configured
645 * - regions configured, but not enabled in the command register
646 * - bogus I/O addresses above 64K used
647 * - expansion ROMs left enabled (this may sound harmless, but given
653 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
668 static void pcibios_allocate_bus_resources(struct pci_bus *bus) in pcibios_allocate_bus_resources() argument
674 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n", in pcibios_allocate_bus_resources()
675 pci_domain_nr(bus), bus->number); in pcibios_allocate_bus_resources()
677 pci_bus_for_each_resource(bus, res, i) { in pcibios_allocate_bus_resources()
678 if (!res || !res->flags in pcibios_allocate_bus_resources()
679 || res->start > res->end || res->parent) in pcibios_allocate_bus_resources()
681 if (bus->parent == NULL) in pcibios_allocate_bus_resources()
682 pr = (res->flags & IORESOURCE_IO) ? in pcibios_allocate_bus_resources()
685 /* Don't bother with non-root busses when in pcibios_allocate_bus_resources()
686 * re-assigning all resources. We clear the in pcibios_allocate_bus_resources()
688 * and as such ensure proper re-allocation in pcibios_allocate_bus_resources()
691 pr = pci_find_parent_resource(bus->self, res); in pcibios_allocate_bus_resources()
695 * bridge is transparent -- paulus in pcibios_allocate_bus_resources()
701 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx ", in pcibios_allocate_bus_resources()
702 bus->self ? pci_name(bus->self) : "PHB", in pcibios_allocate_bus_resources()
703 bus->number, i, in pcibios_allocate_bus_resources()
704 (unsigned long long)res->start, in pcibios_allocate_bus_resources()
705 (unsigned long long)res->end); in pcibios_allocate_bus_resources()
707 (unsigned int)res->flags, in pcibios_allocate_bus_resources()
708 pr, (pr && pr->name) ? pr->name : "nil"); in pcibios_allocate_bus_resources()
710 if (pr && !(pr->flags & IORESOURCE_UNSET)) { in pcibios_allocate_bus_resources()
711 struct pci_dev *dev = bus->self; in pcibios_allocate_bus_resources()
730 pr_cont("%d of PCI bridge %d, will remap\n", i, bus->number); in pcibios_allocate_bus_resources()
731 res->start = res->end = 0; in pcibios_allocate_bus_resources()
732 res->flags = 0; in pcibios_allocate_bus_resources()
735 list_for_each_entry(b, &bus->children, node) in pcibios_allocate_bus_resources()
741 struct resource *pr, *r = &dev->resource[idx]; in alloc_resource()
745 (unsigned long long)r->start, in alloc_resource()
746 (unsigned long long)r->end, in alloc_resource()
747 (unsigned int)r->flags); in alloc_resource()
750 if (!pr || (pr->flags & IORESOURCE_UNSET) || in alloc_resource()
755 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n", in alloc_resource()
757 (unsigned long long)pr->start, in alloc_resource()
758 (unsigned long long)pr->end, in alloc_resource()
759 (unsigned int)pr->flags); in alloc_resource()
761 r->flags |= IORESOURCE_UNSET; in alloc_resource()
762 r->end -= r->start; in alloc_resource()
763 r->start = 0; in alloc_resource()
777 r = &dev->resource[idx]; in pcibios_allocate_resources()
778 if (r->parent) /* Already allocated */ in pcibios_allocate_resources()
780 if (!r->flags || (r->flags & IORESOURCE_UNSET)) in pcibios_allocate_resources()
787 if (r->flags & IORESOURCE_IO) in pcibios_allocate_resources()
796 r = &dev->resource[PCI_ROM_RESOURCE]; in pcibios_allocate_resources()
797 if (r->flags) { in pcibios_allocate_resources()
802 pci_read_config_dword(dev, dev->rom_base_reg, ®); in pcibios_allocate_resources()
806 r->flags &= ~IORESOURCE_ROM_ENABLE; in pcibios_allocate_resources()
807 pci_write_config_dword(dev, dev->rom_base_reg, in pcibios_allocate_resources()
814 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus) in pcibios_reserve_legacy_regions() argument
816 struct pci_controller *hose = pci_bus_to_host(bus); in pcibios_reserve_legacy_regions()
822 pci_domain_nr(bus)); in pcibios_reserve_legacy_regions()
825 if (!(hose->io_resource.flags & IORESOURCE_IO)) in pcibios_reserve_legacy_regions()
827 offset = (unsigned long)hose->io_base_virt - _IO_BASE; in pcibios_reserve_legacy_regions()
830 res->name = "Legacy IO"; in pcibios_reserve_legacy_regions()
831 res->flags = IORESOURCE_IO; in pcibios_reserve_legacy_regions()
832 res->start = offset; in pcibios_reserve_legacy_regions()
833 res->end = (offset + 0xfff) & 0xfffffffful; in pcibios_reserve_legacy_regions()
835 if (request_resource(&hose->io_resource, res)) { in pcibios_reserve_legacy_regions()
837 pci_domain_nr(bus), bus->number, res); in pcibios_reserve_legacy_regions()
843 offset = hose->pci_mem_offset; in pcibios_reserve_legacy_regions()
846 pres = &hose->mem_resources[i]; in pcibios_reserve_legacy_regions()
847 if (!(pres->flags & IORESOURCE_MEM)) in pcibios_reserve_legacy_regions()
850 if ((pres->start - offset) <= 0xa0000 && in pcibios_reserve_legacy_regions()
851 (pres->end - offset) >= 0xbffff) in pcibios_reserve_legacy_regions()
858 res->name = "Legacy VGA memory"; in pcibios_reserve_legacy_regions()
859 res->flags = IORESOURCE_MEM; in pcibios_reserve_legacy_regions()
860 res->start = 0xa0000 + offset; in pcibios_reserve_legacy_regions()
861 res->end = 0xbffff + offset; in pcibios_reserve_legacy_regions()
865 pci_domain_nr(bus), bus->number, res); in pcibios_reserve_legacy_regions()
874 /* Allocate and assign resources. If we re-assign everything, then in pcibios_resource_survey()
885 * bus available resources to avoid allocating things on top of them in pcibios_resource_survey()
903 res = &hose->io_resource; in pcibios_setup_phb_resources()
906 io_offset = (unsigned long)hose->io_base_virt - isa_io_base; in pcibios_setup_phb_resources()
907 res->start = (res->start + io_offset) & 0xffffffffu; in pcibios_setup_phb_resources()
908 res->end = (res->end + io_offset) & 0xffffffffu; in pcibios_setup_phb_resources()
910 if (!res->flags) { in pcibios_setup_phb_resources()
913 hose->dn, hose->global_number); in pcibios_setup_phb_resources()
914 /* Workaround for lack of IO resource only on 32-bit */ in pcibios_setup_phb_resources()
915 res->start = (unsigned long)hose->io_base_virt - isa_io_base; in pcibios_setup_phb_resources()
916 res->end = res->start + IO_SPACE_LIMIT; in pcibios_setup_phb_resources()
917 res->flags = IORESOURCE_IO; in pcibios_setup_phb_resources()
920 (__force resource_size_t)(hose->io_base_virt - _IO_BASE)); in pcibios_setup_phb_resources()
922 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n", in pcibios_setup_phb_resources()
923 (unsigned long long)res->start, in pcibios_setup_phb_resources()
924 (unsigned long long)res->end, in pcibios_setup_phb_resources()
925 (unsigned long)res->flags); in pcibios_setup_phb_resources()
929 res = &hose->mem_resources[i]; in pcibios_setup_phb_resources()
930 if (!res->flags) { in pcibios_setup_phb_resources()
935 hose->dn, hose->global_number); in pcibios_setup_phb_resources()
937 /* Workaround for lack of MEM resource only on 32-bit */ in pcibios_setup_phb_resources()
938 res->start = hose->pci_mem_offset; in pcibios_setup_phb_resources()
939 res->end = (resource_size_t)-1LL; in pcibios_setup_phb_resources()
940 res->flags = IORESOURCE_MEM; in pcibios_setup_phb_resources()
943 pci_add_resource_offset(resources, res, hose->pci_mem_offset); in pcibios_setup_phb_resources()
945 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", in pcibios_setup_phb_resources()
946 i, (unsigned long long)res->start, in pcibios_setup_phb_resources()
947 (unsigned long long)res->end, in pcibios_setup_phb_resources()
948 (unsigned long)res->flags); in pcibios_setup_phb_resources()
952 (unsigned long long)hose->pci_mem_offset); in pcibios_setup_phb_resources()
954 (unsigned long)hose->io_base_virt - _IO_BASE); in pcibios_setup_phb_resources()
960 struct pci_bus *bus; in pcibios_scan_phb() local
961 struct device_node *node = hose->dn; in pcibios_scan_phb()
967 bus = pci_scan_root_bus(hose->parent, hose->first_busno, in pcibios_scan_phb()
968 hose->ops, hose, &resources); in pcibios_scan_phb()
969 if (bus == NULL) { in pcibios_scan_phb()
970 pr_err("Failed to create bus for PCI domain %04x\n", in pcibios_scan_phb()
971 hose->global_number); in pcibios_scan_phb()
975 bus->busn_res.start = hose->first_busno; in pcibios_scan_phb()
976 hose->bus = bus; in pcibios_scan_phb()
978 hose->last_busno = bus->busn_res.end; in pcibios_scan_phb()
990 hose->last_busno = 0xff; in pcibios_init()
992 if (next_busno <= hose->last_busno) in pcibios_init()
993 next_busno = hose->last_busno + 1; in pcibios_init()
1000 if (hose->bus) in pcibios_init()
1001 pci_bus_add_devices(hose->bus); in pcibios_init()
1009 static struct pci_controller *pci_bus_to_hose(int bus) in pci_bus_to_hose() argument
1014 if (bus >= hose->first_busno && bus <= hose->last_busno) in pci_bus_to_hose()
1020 * memory. Do this on a per-card basis so that we choose the right
1025 long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn) in sys_pciconfig_iobase() argument
1028 long result = -EOPNOTSUPP; in sys_pciconfig_iobase()
1030 hose = pci_bus_to_hose(bus); in sys_pciconfig_iobase()
1032 return -ENODEV; in sys_pciconfig_iobase()
1036 return (long)hose->first_busno; in sys_pciconfig_iobase()
1038 return (long)hose->pci_mem_offset; in sys_pciconfig_iobase()
1040 return (long)hose->io_base_phys; in sys_pciconfig_iobase()
1062 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, in null_read_config() argument
1069 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, in null_write_config() argument
1087 static struct pci_bus bus; in fake_pci_bus() local
1090 pr_err("Can't find hose for PCI bus %d!\n", busnr); in fake_pci_bus()
1092 bus.number = busnr; in fake_pci_bus()
1093 bus.sysdata = hose; in fake_pci_bus()
1094 bus.ops = hose ? hose->ops : &null_pci_ops; in fake_pci_bus()
1095 return &bus; in fake_pci_bus()
1099 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1102 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1113 int early_find_capability(struct pci_controller *hose, int bus, int devfn, in EARLY_PCI_OP()
1116 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap); in EARLY_PCI_OP()