Lines Matching refs:cmcv
640 cmcv_reg_t cmcv; in ia64_mca_cmc_vector_setup() local
642 cmcv.cmcv_regval = 0; in ia64_mca_cmc_vector_setup()
643 cmcv.cmcv_mask = 1; /* Mask/disable interrupt at first */ in ia64_mca_cmc_vector_setup()
644 cmcv.cmcv_vector = IA64_CMC_VECTOR; in ia64_mca_cmc_vector_setup()
645 ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval); in ia64_mca_cmc_vector_setup()
669 cmcv_reg_t cmcv; in ia64_mca_cmc_vector_disable() local
671 cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV); in ia64_mca_cmc_vector_disable()
673 cmcv.cmcv_mask = 1; /* Mask/disable interrupt */ in ia64_mca_cmc_vector_disable()
674 ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval); in ia64_mca_cmc_vector_disable()
677 __func__, smp_processor_id(), cmcv.cmcv_vector); in ia64_mca_cmc_vector_disable()
695 cmcv_reg_t cmcv; in ia64_mca_cmc_vector_enable() local
697 cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV); in ia64_mca_cmc_vector_enable()
699 cmcv.cmcv_mask = 0; /* Unmask/enable interrupt */ in ia64_mca_cmc_vector_enable()
700 ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval); in ia64_mca_cmc_vector_enable()
703 __func__, smp_processor_id(), cmcv.cmcv_vector); in ia64_mca_cmc_vector_enable()