Lines Matching +full:non +full:- +full:zero

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * Copyright (c) 2012-2021, Arm Limited.
6  * https://github.com/ARM-software/optimized-routines/blob/afd6244a1f8d9229/string/aarch64/strcmp.S
14  * ARMv8-a, AArch64
42 	/* Start of performance-critical section  -- one 64B cache line.  */
51 	/* NUL detection works on the principle that (X - 1) & (~X) & 0x80
52 	   (=> (X - 1) & ~(X | 0x7f)) is non-zero iff a byte is zero, and
60 	eor	diff, data1, data2	/* Non-zero if differences found.  */
61 	bic	has_nul, tmp1, tmp2	/* Non-zero if NUL terminator.  */
64 	/* End of performance-critical section  -- one 64B cache line.  */
70 	/* The MS-non-zero bit of the syndrome marks either the first bit
71 	   that is different, or the top bit of the first zero byte.
78 	/* But we need to zero-extend (char is unsigned) the value and then
79 	   perform a signed 32-bit subtraction.  */
84 	/* For big-endian we cannot use the trick with the syndrome value
85 	   as carry-propagation can corrupt the upper bits if the trailing
96 	/* Re-compute the NUL-byte detection, using a byte-reversed value.  */
104 	/* The MS-non-zero bit of the syndrome marks either the first bit
105 	   that is different, or the top bit of the first zero byte.
110 	/* But we need to zero-extend (char is unsigned) the value and then
111 	   perform a signed 32-bit subtraction.  */
123 	lsl	tmp1, tmp1, #3		/* Bytes beyond alignment -> bits.  */
125 	neg	tmp1, tmp1		/* Bits to alignment -64.  */
129 	/* Big-endian.  Early bytes are at MSB.  */
132 	/* Little-endian.  Early bytes are at LSB.  */
165 	eor	diff, data1, data2	/* Non-zero if differences found.  */
166 	bic	has_nul, tmp1, tmp2	/* Non-zero if NUL terminator.  */