61  * This performs the exception entry at a given EL (@target_mode), stashing PC
66  * When an exception is taken, most PSTATE fields are left unchanged in the
120 	// PSTATE.UAO is set to zero upon any exception to AArch64  in enter_exception64()
130 	// PSTATE.SS is set to zero upon any exception to AArch64  in enter_exception64()
133 	// PSTATE.IL is set to zero upon any exception to AArch64  in enter_exception64()
136 	// PSTATE.SSBS is set to SCTLR_ELx.DSSBS upon any exception to AArch64  in enter_exception64()
141 	// PSTATE.BTYPE is set to zero upon any exception to AArch64  in enter_exception64()
156  * When an exception is taken, most CPSR fields are left unchanged in the
187 	// CPSR.IT[7:0] are set to zero upon any exception  in get_except32_cpsr()
193 	// CPSR.SSBS is set to SCTLR.DSSBS upon any exception  in get_except32_cpsr()
207 	// CPSR.IL is set to zero upon any exception  in get_except32_cpsr()
212 	// CPSR.IT[7:0] are set to zero upon any exception  in get_except32_cpsr()
215 	// CPSR.E is set to SCTLR.EE upon any exception  in get_except32_cpsr()
221 	// CPSR.A is unchanged upon an exception to Undefined, Supervisor  in get_except32_cpsr()
222 	// CPSR.A is set upon an exception to other modes  in get_except32_cpsr()
229 	// CPSR.I is set upon any exception  in get_except32_cpsr()
234 	// CPSR.F is set upon an exception to FIQ  in get_except32_cpsr()
235 	// CPSR.F is unchanged upon an exception to other modes  in get_except32_cpsr()
242 	// CPSR.T is set to SCTLR.TE upon any exception  in get_except32_cpsr()
291 	/* Branch to exception vector */  in enter_exception32()
335  * Adjust the guest PC (and potentially exception state) depending on