Lines Matching refs:tmp1
137 .macro create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2
138 add \tmp1, \tbl, #PAGE_SIZE
139 phys_to_pte \tmp2, \tmp1
141 lsr \tmp1, \virt, #\shift
143 and \tmp1, \tmp1, \ptrs // table index
144 str \tmp2, [\tbl, \tmp1, lsl #3]
164 .macro populate_entries, tbl, rtbl, index, eindex, flags, inc, tmp1
165 .Lpe\@: phys_to_pte \tmp1, \rtbl
166 orr \tmp1, \tmp1, \flags // tmp1 = table entry
167 str \tmp1, [\tbl, \index, lsl #3]
402 .macro init_cpu_task tsk, tmp1, tmp2
405 ldr \tmp1, [\tsk, #TSK_STACK]
406 add sp, \tmp1, #THREAD_SIZE
414 adr_l \tmp1, __per_cpu_offset
416 ldr \tmp1, [\tmp1, \tmp2, lsl #3]
417 set_this_cpu_offset \tmp1
681 .macro update_early_cpu_boot_status status, tmp1, tmp2
683 adr_l \tmp1, __early_cpu_boot_status
684 str \tmp2, [\tmp1]
686 dc ivac, \tmp1 // Invalidate potentially stale cache line