Lines Matching +full:0 +full:x29

33 	.irp	n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29
41 	.if	\el == 0
62 	tbnz	x0, #THREAD_SHIFT, 0f
67 0:
120 	nop					// Patched to SMC/HVC #0
196 	stp	x0, x1, [sp, #16 * 0]
210 	stp	x28, x29, [sp, #16 * 14]
212 	.if	\el == 0
272 	.endif /* \el == 0 */
282 	.if \el == 0
285 	stp	x29, x22, [sp, #S_STACKFRAME]
287 	add	x29, sp, #S_STACKFRAME
298 	.if	\el == 0
314 	SET_PSTATE_TCO(0)
329 	.if	\el != 0
351 	.if	\el == 0
360 	mrs	x29, contextidr_el1
361 	msr	contextidr_el1, x29
396 	apply_ssbd 0, x0, x1
401 	ldp	x0, x1, [sp, #16 * 0]
415 	ldp	x28, x29, [sp, #16 * 14]
419 	.if	\el == 0
466 1:	and	x22, x22, #~PSR_PAN_BIT		// ARMv8.0 CPUs do not understand this bit
504 	kernel_ventry	0, t, 64, sync		// Synchronous 64-bit EL0
505 	kernel_ventry	0, t, 64, irq		// IRQ 64-bit EL0
506 	kernel_ventry	0, t, 64, fiq		// FIQ 64-bit EL0
507 	kernel_ventry	0, t, 64, error		// Error 64-bit EL0
509 	kernel_ventry	0, t, 32, sync		// Synchronous 32-bit EL0
510 	kernel_ventry	0, t, 32, irq		// IRQ 32-bit EL0
511 	kernel_ventry	0, t, 32, fiq		// FIQ 32-bit EL0
512 	kernel_ventry	0, t, 32, error		// Error 32-bit EL0
551 	.if \el == 0
572 	entry_handler	0, t, 64, sync
573 	entry_handler	0, t, 64, irq
574 	entry_handler	0, t, 64, fiq
575 	entry_handler	0, t, 64, error
577 	entry_handler	0, t, 32, sync
578 	entry_handler	0, t, 32, irq
579 	entry_handler	0, t, 32, fiq
580 	entry_handler	0, t, 32, error
592 	kernel_exit 0
680 	.space	0x400
730 	stp	x29, x9, [x8], #16
738 	ldp	x29, x9, [x8], #16
776 	stp	x29, x30, [sp, #-16]!
777 	mov	x29, sp
791 	mov	sp, x29
792 	ldp	x29, x30, [sp], #16
809 	smc	#0
811 99:	hvc	#0
904 	stp     x28, x29, [x1, #SDEI_EVENT_INTREGS + 16 * 14]
947 	and     x0, x3, #0xc
950 	csel	x29, x29, xzr, eq	// fp, or zero
953 	stp	x29, x4, [sp, #-16]!
954 	mov	x29, sp
963 	ldp	x28, x29, [x4, #SDEI_EVENT_INTREGS + 16 * 14]