Lines Matching +full:0 +full:x21

33 	.irp	n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29
41 	.if	\el == 0
62 	tbnz	x0, #THREAD_SHIFT, 0f
67 0:
120 	nop					// Patched to SMC/HVC #0
196 	stp	x0, x1, [sp, #16 * 0]
206 	stp	x20, x21, [sp, #16 * 10]
212 	.if	\el == 0
214 	mrs	x21, sp_el0
270 	add	x21, sp, #PT_REGS_SIZE
272 	.endif /* \el == 0 */
275 	stp	lr, x21, [sp, #S_LR]
282 	.if \el == 0
298 	.if	\el == 0
314 	SET_PSTATE_TCO(0)
322 	 * x21 - aborted SP
329 	.if	\el != 0
337 	mrs_s	x21, SYS_ICC_CTLR_EL1
338 	tbz	x21, #6, .L__skip_pmr_sync\@	// Check for ICC_CTLR_EL1.PMHE
343 	ldp	x21, x22, [sp, #S_PC]		// load ELR, SPSR
351 	.if	\el == 0
396 	apply_ssbd 0, x0, x1
399 	msr	elr_el1, x21			// set up the return data
401 	ldp	x0, x1, [sp, #16 * 0]
411 	ldp	x20, x21, [sp, #16 * 10]
419 	.if	\el == 0
449 	mrs	x21, ttbr0_el1
450 	tst	x21, #TTBR_ASID_MASK		// Check for the reserved ASID
455 	__uaccess_ttbr0_disable x21
466 1:	and	x22, x22, #~PSR_PAN_BIT		// ARMv8.0 CPUs do not understand this bit
504 	kernel_ventry	0, t, 64, sync		// Synchronous 64-bit EL0
505 	kernel_ventry	0, t, 64, irq		// IRQ 64-bit EL0
506 	kernel_ventry	0, t, 64, fiq		// FIQ 64-bit EL0
507 	kernel_ventry	0, t, 64, error		// Error 64-bit EL0
509 	kernel_ventry	0, t, 32, sync		// Synchronous 32-bit EL0
510 	kernel_ventry	0, t, 32, irq		// IRQ 32-bit EL0
511 	kernel_ventry	0, t, 32, fiq		// FIQ 32-bit EL0
512 	kernel_ventry	0, t, 32, error		// Error 32-bit EL0
551 	.if \el == 0
572 	entry_handler	0, t, 64, sync
573 	entry_handler	0, t, 64, irq
574 	entry_handler	0, t, 64, fiq
575 	entry_handler	0, t, 64, error
577 	entry_handler	0, t, 32, sync
578 	entry_handler	0, t, 32, irq
579 	entry_handler	0, t, 32, fiq
580 	entry_handler	0, t, 32, error
592 	kernel_exit 0
680 	.space	0x400
726 	stp	x21, x22, [x8], #16
734 	ldp	x21, x22, [x8], #16
809 	smc	#0
811 99:	hvc	#0
900 	stp     x20, x21, [x1, #SDEI_EVENT_INTREGS + 16 * 10]
947 	and     x0, x3, #0xc