Lines Matching +full:0 +full:x19
33 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29
41 .if \el == 0
62 tbnz x0, #THREAD_SHIFT, 0f
67 0:
120 nop // Patched to SMC/HVC #0
196 stp x0, x1, [sp, #16 * 0]
205 stp x18, x19, [sp, #16 * 9]
212 .if \el == 0
222 ldr x19, [tsk, #TSK_TI_FLAGS]
223 disable_step_tsk x19, x20
272 .endif /* \el == 0 */
282 .if \el == 0
298 .if \el == 0
314 SET_PSTATE_TCO(0)
329 .if \el != 0
351 .if \el == 0
396 apply_ssbd 0, x0, x1
401 ldp x0, x1, [sp, #16 * 0]
410 ldp x18, x19, [sp, #16 * 9]
419 .if \el == 0
466 1: and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit
504 kernel_ventry 0, t, 64, sync // Synchronous 64-bit EL0
505 kernel_ventry 0, t, 64, irq // IRQ 64-bit EL0
506 kernel_ventry 0, t, 64, fiq // FIQ 64-bit EL0
507 kernel_ventry 0, t, 64, error // Error 64-bit EL0
509 kernel_ventry 0, t, 32, sync // Synchronous 32-bit EL0
510 kernel_ventry 0, t, 32, irq // IRQ 32-bit EL0
511 kernel_ventry 0, t, 32, fiq // FIQ 32-bit EL0
512 kernel_ventry 0, t, 32, error // Error 32-bit EL0
551 .if \el == 0
572 entry_handler 0, t, 64, sync
573 entry_handler 0, t, 64, irq
574 entry_handler 0, t, 64, fiq
575 entry_handler 0, t, 64, error
577 entry_handler 0, t, 32, sync
578 entry_handler 0, t, 32, irq
579 entry_handler 0, t, 32, fiq
580 entry_handler 0, t, 32, error
587 ldr x19, [tsk, #TSK_TI_FLAGS] // re-check for single-step
588 enable_step_tsk x19, x2
592 kernel_exit 0
680 .space 0x400
725 stp x19, x20, [x8], #16 // store callee-saved registers
733 ldp x19, x20, [x8], #16 // restore callee-saved registers
754 cbz x19, 1f // not a kernel thread
756 blr x19
809 smc #0
811 99: hvc #0
899 stp x18, x19, [x1, #SDEI_EVENT_INTREGS + 16 * 9]
908 mov x19, x1
911 ldrb w4, [x19, #SDEI_EVENT_PRIORITY]
947 and x0, x3, #0xc
956 add x0, x19, #SDEI_EVENT_INTREGS
957 mov x1, x19
962 mov x4, x19 // keep x4 for __sdei_asm_exit_trampoline
964 ldp x18, x19, [x4, #SDEI_EVENT_INTREGS + 16 * 9]