Lines Matching +full:12 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
20 * [20-19] : Op0
21 * [18-16] : Op1
22 * [15-12] : CRn
23 * [11-8] : CRm
24 * [7-5] : Op2
30 #define CRn_shift 12
81 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
237 #define SYS_PAR_EL1_F BIT(0)
251 #define SYS_PMSIDR_EL1_MAXSIZE_SHIFT 12
351 #define TRBLIMITR_LIMIT_SHIFT 12
352 #define TRBLIMITR_NVM BIT(5)
357 #define TRBLIMITR_ENABLE BIT(0)
361 #define TRBBASER_BASE_SHIFT 12
364 #define TRBSR_IRQ BIT(22)
365 #define TRBSR_TRG BIT(21)
366 #define TRBSR_WRAP BIT(20)
367 #define TRBSR_ABORT BIT(18)
368 #define TRBSR_STOP BIT(17)
383 #define TRBIDR_FLAG BIT(5)
384 #define TRBIDR_PROG BIT(4)
402 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
403 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1)
405 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0)
406 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
407 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
408 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
409 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n)
414 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n)
419 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
420 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3)
421 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
422 #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6)
423 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7)
424 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
425 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
426 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2)
427 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
428 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
429 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
430 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6)
431 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
453 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
454 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
455 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
456 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
457 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
458 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5)
459 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
460 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
488 * n: 0-15
494 * n: 0-15
499 #define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
548 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
549 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
555 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
561 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
562 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
563 #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
564 #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
565 #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
566 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
567 #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5)
568 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
570 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
580 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
606 #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
617 #define SCTLR_ELx_DSSBS (BIT(44))
618 #define SCTLR_ELx_ATA (BIT(43))
628 #define SCTLR_ELx_ITFSB (BIT(37))
629 #define SCTLR_ELx_ENIA (BIT(SCTLR_ELx_ENIA_SHIFT))
630 #define SCTLR_ELx_ENIB (BIT(30))
631 #define SCTLR_ELx_ENDA (BIT(27))
632 #define SCTLR_ELx_EE (BIT(25))
633 #define SCTLR_ELx_IESB (BIT(21))
634 #define SCTLR_ELx_WXN (BIT(19))
635 #define SCTLR_ELx_ENDB (BIT(13))
636 #define SCTLR_ELx_I (BIT(12))
637 #define SCTLR_ELx_SA (BIT(3))
638 #define SCTLR_ELx_C (BIT(2))
639 #define SCTLR_ELx_A (BIT(1))
640 #define SCTLR_ELx_M (BIT(0))
643 #define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \
644 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \
645 (BIT(29)))
662 #define SCTLR_EL1_EPAN (BIT(57))
663 #define SCTLR_EL1_ATA0 (BIT(42))
671 #define SCTLR_EL1_BT1 (BIT(36))
672 #define SCTLR_EL1_BT0 (BIT(35))
673 #define SCTLR_EL1_UCI (BIT(26))
674 #define SCTLR_EL1_E0E (BIT(24))
675 #define SCTLR_EL1_SPAN (BIT(23))
676 #define SCTLR_EL1_NTWE (BIT(18))
677 #define SCTLR_EL1_NTWI (BIT(16))
678 #define SCTLR_EL1_UCT (BIT(15))
679 #define SCTLR_EL1_DZE (BIT(14))
680 #define SCTLR_EL1_UMA (BIT(9))
681 #define SCTLR_EL1_SED (BIT(8))
682 #define SCTLR_EL1_ITD (BIT(7))
683 #define SCTLR_EL1_CP15BEN (BIT(5))
684 #define SCTLR_EL1_SA0 (BIT(4))
686 #define SCTLR_EL1_RES1 ((BIT(11)) | (BIT(20)) | (BIT(22)) | (BIT(28)) | \
687 (BIT(29)))
727 #define ID_AA64ISAR0_SHA2_SHIFT 12
745 #define ID_AA64ISAR1_JSCVT_SHIFT 12
779 #define ID_AA64PFR0_EL3_SHIFT 12
797 #define ID_AA64PFR1_RASFRAC_SHIFT 12
844 #define ID_AA64MMFR0_SNSMEM_SHIFT 12
890 #define ID_AA64MMFR1_HPD_SHIFT 12
910 #define ID_AA64MMFR2_IESB_SHIFT 12
923 #define ID_AA64DFR0_BRPS_SHIFT 12
948 #define ID_ISAR4_SMC_SHIFT 12
958 #define ID_ISAR0_CMPBRANCH_SHIFT 12
965 #define ID_ISAR5_SHA2_SHIFT 12
973 #define ID_ISAR6_SB_SHIFT 12
982 #define ID_MMFR0_SHARELVL_SHIFT 12
991 #define ID_MMFR4_CNP_SHIFT 12
1000 #define ID_PFR0_STATE3_SHIFT 12
1008 #define ID_DFR0_COPTRC_SHIFT 12
1020 #define MVFR0_FPTRAP_SHIFT 12
1029 #define MVFR1_SIMDINT_SHIFT 12
1038 #define ID_PFR1_VIRTUALIZATION_SHIFT 12
1075 #define CPACR_EL1_ZEN_EL1EN (BIT(16)) /* enable EL1 access */
1076 #define CPACR_EL1_ZEN_EL0EN (BIT(17)) /* enable EL0 access, if EL1EN set */
1079 /* TCR EL1 Bit Definitions */
1080 #define SYS_TCR_EL1_TCMA1 (BIT(58))
1081 #define SYS_TCR_EL1_TCMA0 (BIT(57))
1084 #define SYS_GCR_EL1_RRND (BIT(16))
1090 * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
1111 /* TFSR{,E0}_EL1 bit definitions */
1118 #define SYS_MPIDR_SAFE_VAL (BIT(31))
1124 #define TRFCR_EL2_CX BIT(3)
1125 #define TRFCR_ELx_ExTRE BIT(1)
1126 #define TRFCR_ELx_E0TRE BIT(0)
1130 /* ICH_MISR_EL2 bit definitions */
1134 /* ICH_LR*_EL2 bit definitions */
1135 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
1148 /* ICH_HCR_EL2 bit definitions */
1154 #define ICH_HCR_TALL1 (1 << 12)
1158 /* ICH_VMCR_EL2 bit definitions */
1178 /* ICH_VTR_EL2 bit definitions */
1191 #define ARM64_FEATURE_MASK(x) (GENMASK_ULL(x##_SHIFT + ARM64_FEATURE_FIELD_BITS - 1, x##_SHIFT))
1195 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
1215 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" \
1285 * set mask are set. Other bits are left as-is.