Lines Matching refs:x0
20 mov_q x0, INIT_SCTLR_EL2_MMU_OFF
21 msr sctlr_el2, x0
36 mov x0, #3 // Enable EL1 physical timers
37 msr cnthctl_el2, x0
43 sbfx x0, x1, #ID_AA64DFR0_PMUVER_SHIFT, #4
44 cmp x0, #1
46 mrs x0, pmcr_el0 // Disable debug access traps
47 ubfx x0, x0, #11, #5 // to EL2 and allow access to
49 csel x2, xzr, x0, lt // all PMU counters from EL1
52 ubfx x0, x1, #ID_AA64DFR0_PMSVER_SHIFT, #4
53 cbz x0, .Lskip_spe_\@ // Skip if SPE not present
55 mrs_s x0, SYS_PMBIDR_EL1 // If SPE available at EL2,
56 and x0, x0, #(1 << SYS_PMBIDR_EL1_P_SHIFT)
57 cbnz x0, .Lskip_spe_el2_\@ // then permit sampling of physical
58 mov x0, #(1 << SYS_PMSCR_EL2_PCT_SHIFT | \
60 msr_s SYS_PMSCR_EL2, x0 // addresses and physical counter
62 mov x0, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT)
63 orr x2, x2, x0 // If we don't have VHE, then
68 ubfx x0, x1, #ID_AA64DFR0_TRBE_SHIFT, #4
69 cbz x0, .Lskip_trace_\@ // Skip if TraceBuffer is not present
71 mrs_s x0, SYS_TRBIDR_EL1
72 and x0, x0, TRBIDR_PROG
73 cbnz x0, .Lskip_trace_\@ // If TRBE is available at EL2
75 mov x0, #(MDCR_EL2_E2TB_MASK << MDCR_EL2_E2TB_SHIFT)
76 orr x2, x2, x0 // allow the EL1&0 translation
86 ubfx x0, x1, #ID_AA64MMFR1_LOR_SHIFT, 4
87 cbz x0, .Lskip_lor_\@
99 mrs x0, id_aa64pfr0_el1
100 ubfx x0, x0, #ID_AA64PFR0_GIC_SHIFT, #4
101 cbz x0, .Lskip_gicv3_\@
103 mrs_s x0, SYS_ICC_SRE_EL2
104 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1
105 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1
106 msr_s SYS_ICC_SRE_EL2, x0
108 mrs_s x0, SYS_ICC_SRE_EL2 // Read SRE back,
109 tbz x0, #0, 1f // and check that it sticks
120 mrs x0, midr_el1
122 msr vpidr_el2, x0
128 mov x0, #0x33ff
129 msr cptr_el2, x0 // Disable copro. traps to EL2
138 bic x0, x0, #CPTR_EL2_TZ // Also disable SVE traps
139 msr cptr_el2, x0 // Disable copro. traps to EL2
152 mov x0, xzr
158 orr x0, x0, #(1 << 62)
161 msr_s SYS_HDFGRTR_EL2, x0
162 msr_s SYS_HDFGWTR_EL2, x0
176 mov x0, #INIT_PSTATE_EL1
177 msr spsr_el2, x0