Lines Matching +full:zynqmp +full:- +full:qspi +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP
5 * (C) Copyright 2014 - 2019, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/power/xlnx-zynqmp-power.h>
17 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
20 compatible = "xlnx,zynqmp";
21 #address-cells = <2>;
22 #size-cells = <2>;
25 #address-cells = <1>;
26 #size-cells = <0>;
29 compatible = "arm,cortex-a53";
31 enable-method = "psci";
32 operating-points-v2 = <&cpu_opp_table>;
34 cpu-idle-states = <&CPU_SLEEP_0>;
37 cpu1: cpu@1 {
38 compatible = "arm,cortex-a53";
40 enable-method = "psci";
42 operating-points-v2 = <&cpu_opp_table>;
43 cpu-idle-states = <&CPU_SLEEP_0>;
47 compatible = "arm,cortex-a53";
49 enable-method = "psci";
51 operating-points-v2 = <&cpu_opp_table>;
52 cpu-idle-states = <&CPU_SLEEP_0>;
56 compatible = "arm,cortex-a53";
58 enable-method = "psci";
60 operating-points-v2 = <&cpu_opp_table>;
61 cpu-idle-states = <&CPU_SLEEP_0>;
64 idle-states {
65 entry-method = "psci";
67 CPU_SLEEP_0: cpu-sleep-0 {
68 compatible = "arm,idle-state";
69 arm,psci-suspend-param = <0x40000000>;
70 local-timer-stop;
71 entry-latency-us = <300>;
72 exit-latency-us = <600>;
73 min-residency-us = <10000>;
78 cpu_opp_table: cpu-opp-table {
79 compatible = "operating-points-v2";
80 opp-shared;
82 opp-hz = /bits/ 64 <1199999988>;
83 opp-microvolt = <1000000>;
84 clock-latency-ns = <500000>;
87 opp-hz = /bits/ 64 <599999994>;
88 opp-microvolt = <1000000>;
89 clock-latency-ns = <500000>;
92 opp-hz = /bits/ 64 <399999996>;
93 opp-microvolt = <1000000>;
94 clock-latency-ns = <500000>;
97 opp-hz = /bits/ 64 <299999997>;
98 opp-microvolt = <1000000>;
99 clock-latency-ns = <500000>;
104 compatible = "xlnx,zynqmp-ipi-mailbox";
105 interrupt-parent = <&gic>;
107 xlnx,ipi-id = <0>;
108 #address-cells = <2>;
109 #size-cells = <2>;
117 reg-names = "local_request_region",
121 #mbox-cells = <1>;
122 xlnx,ipi-id = <4>;
132 compatible = "arm,armv8-pmuv3";
133 interrupt-parent = <&gic>;
141 compatible = "arm,psci-0.2";
146 zynqmp_firmware: zynqmp-firmware {
147 compatible = "xlnx,zynqmp-firmware";
148 #power-domain-cells = <1>;
151 zynqmp_power: zynqmp-power {
152 compatible = "xlnx,zynqmp-power";
153 interrupt-parent = <&gic>;
155 mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>;
156 mbox-names = "tx", "rx";
159 zynqmp_clk: clock-controller {
160 #clock-cells = <1>;
161 compatible = "xlnx,zynqmp-clk";
167 clock-names = "pss_ref_clk",
175 compatible = "xlnx,zynqmp-nvmem-fw";
176 #address-cells = <1>;
177 #size-cells = <1>;
185 compatible = "xlnx,zynqmp-pcap-fpga";
188 xlnx_aes: zynqmp-aes {
189 compatible = "xlnx,zynqmp-aes";
192 zynqmp_reset: reset-controller {
193 compatible = "xlnx,zynqmp-reset";
194 #reset-cells = <1>;
200 compatible = "arm,armv8-timer";
201 interrupt-parent = <&gic>;
202 interrupts = <1 13 0xf08>,
203 <1 14 0xf08>,
204 <1 11 0xf08>,
205 <1 10 0xf08>;
208 fpga_full: fpga-full {
209 compatible = "fpga-region";
210 fpga-mgr = <&zynqmp_pcap>;
211 #address-cells = <2>;
212 #size-cells = <2>;
217 compatible = "simple-bus";
218 #address-cells = <2>;
219 #size-cells = <2>;
223 compatible = "xlnx,zynq-can-1.0";
225 clock-names = "can_clk", "pclk";
228 interrupt-parent = <&gic>;
229 tx-fifo-depth = <0x40>;
230 rx-fifo-depth = <0x40>;
231 power-domains = <&zynqmp_firmware PD_CAN_0>;
235 compatible = "xlnx,zynq-can-1.0";
237 clock-names = "can_clk", "pclk";
240 interrupt-parent = <&gic>;
241 tx-fifo-depth = <0x40>;
242 rx-fifo-depth = <0x40>;
243 power-domains = <&zynqmp_firmware PD_CAN_1>;
247 compatible = "arm,cci-400";
250 #address-cells = <1>;
251 #size-cells = <1>;
254 compatible = "arm,cci-400-pmu,r1";
256 interrupt-parent = <&gic>;
268 compatible = "xlnx,zynqmp-dma-1.0";
270 interrupt-parent = <&gic>;
272 clock-names = "clk_main", "clk_apb";
273 xlnx,bus-width = <128>;
274 #stream-id-cells = <1>;
276 power-domains = <&zynqmp_firmware PD_GDMA>;
281 compatible = "xlnx,zynqmp-dma-1.0";
283 interrupt-parent = <&gic>;
285 clock-names = "clk_main", "clk_apb";
286 xlnx,bus-width = <128>;
287 #stream-id-cells = <1>;
289 power-domains = <&zynqmp_firmware PD_GDMA>;
294 compatible = "xlnx,zynqmp-dma-1.0";
296 interrupt-parent = <&gic>;
298 clock-names = "clk_main", "clk_apb";
299 xlnx,bus-width = <128>;
300 #stream-id-cells = <1>;
302 power-domains = <&zynqmp_firmware PD_GDMA>;
307 compatible = "xlnx,zynqmp-dma-1.0";
309 interrupt-parent = <&gic>;
311 clock-names = "clk_main", "clk_apb";
312 xlnx,bus-width = <128>;
313 #stream-id-cells = <1>;
315 power-domains = <&zynqmp_firmware PD_GDMA>;
320 compatible = "xlnx,zynqmp-dma-1.0";
322 interrupt-parent = <&gic>;
324 clock-names = "clk_main", "clk_apb";
325 xlnx,bus-width = <128>;
326 #stream-id-cells = <1>;
328 power-domains = <&zynqmp_firmware PD_GDMA>;
333 compatible = "xlnx,zynqmp-dma-1.0";
335 interrupt-parent = <&gic>;
337 clock-names = "clk_main", "clk_apb";
338 xlnx,bus-width = <128>;
339 #stream-id-cells = <1>;
341 power-domains = <&zynqmp_firmware PD_GDMA>;
346 compatible = "xlnx,zynqmp-dma-1.0";
348 interrupt-parent = <&gic>;
350 clock-names = "clk_main", "clk_apb";
351 xlnx,bus-width = <128>;
352 #stream-id-cells = <1>;
354 power-domains = <&zynqmp_firmware PD_GDMA>;
359 compatible = "xlnx,zynqmp-dma-1.0";
361 interrupt-parent = <&gic>;
363 clock-names = "clk_main", "clk_apb";
364 xlnx,bus-width = <128>;
365 #stream-id-cells = <1>;
367 power-domains = <&zynqmp_firmware PD_GDMA>;
370 gic: interrupt-controller@f9010000 {
371 compatible = "arm,gic-400";
372 #address-cells = <0>;
373 #interrupt-cells = <3>;
378 interrupt-controller;
379 interrupt-parent = <&gic>;
380 interrupts = <1 9 0xf04>;
389 compatible = "xlnx,zynqmp-dma-1.0";
391 interrupt-parent = <&gic>;
393 clock-names = "clk_main", "clk_apb";
394 xlnx,bus-width = <64>;
395 #stream-id-cells = <1>;
397 power-domains = <&zynqmp_firmware PD_ADMA>;
402 compatible = "xlnx,zynqmp-dma-1.0";
404 interrupt-parent = <&gic>;
406 clock-names = "clk_main", "clk_apb";
407 xlnx,bus-width = <64>;
408 #stream-id-cells = <1>;
410 power-domains = <&zynqmp_firmware PD_ADMA>;
415 compatible = "xlnx,zynqmp-dma-1.0";
417 interrupt-parent = <&gic>;
419 clock-names = "clk_main", "clk_apb";
420 xlnx,bus-width = <64>;
421 #stream-id-cells = <1>;
423 power-domains = <&zynqmp_firmware PD_ADMA>;
428 compatible = "xlnx,zynqmp-dma-1.0";
430 interrupt-parent = <&gic>;
432 clock-names = "clk_main", "clk_apb";
433 xlnx,bus-width = <64>;
434 #stream-id-cells = <1>;
436 power-domains = <&zynqmp_firmware PD_ADMA>;
441 compatible = "xlnx,zynqmp-dma-1.0";
443 interrupt-parent = <&gic>;
445 clock-names = "clk_main", "clk_apb";
446 xlnx,bus-width = <64>;
447 #stream-id-cells = <1>;
449 power-domains = <&zynqmp_firmware PD_ADMA>;
454 compatible = "xlnx,zynqmp-dma-1.0";
456 interrupt-parent = <&gic>;
458 clock-names = "clk_main", "clk_apb";
459 xlnx,bus-width = <64>;
460 #stream-id-cells = <1>;
462 power-domains = <&zynqmp_firmware PD_ADMA>;
467 compatible = "xlnx,zynqmp-dma-1.0";
469 interrupt-parent = <&gic>;
471 clock-names = "clk_main", "clk_apb";
472 xlnx,bus-width = <64>;
473 #stream-id-cells = <1>;
475 power-domains = <&zynqmp_firmware PD_ADMA>;
480 compatible = "xlnx,zynqmp-dma-1.0";
482 interrupt-parent = <&gic>;
484 clock-names = "clk_main", "clk_apb";
485 xlnx,bus-width = <64>;
486 #stream-id-cells = <1>;
488 power-domains = <&zynqmp_firmware PD_ADMA>;
491 mc: memory-controller@fd070000 {
492 compatible = "xlnx,zynqmp-ddrc-2.40a";
494 interrupt-parent = <&gic>;
498 nand0: nand-controller@ff100000 {
499 compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10";
502 clock-names = "controller", "bus";
503 interrupt-parent = <&gic>;
505 #address-cells = <1>;
506 #size-cells = <0>;
507 #stream-id-cells = <1>;
509 power-domains = <&zynqmp_firmware PD_NAND>;
513 compatible = "cdns,zynqmp-gem", "cdns,gem";
515 interrupt-parent = <&gic>;
518 clock-names = "pclk", "hclk", "tx_clk";
519 #address-cells = <1>;
520 #size-cells = <0>;
521 #stream-id-cells = <1>;
523 power-domains = <&zynqmp_firmware PD_ETH_0>;
527 compatible = "cdns,zynqmp-gem", "cdns,gem";
529 interrupt-parent = <&gic>;
532 clock-names = "pclk", "hclk", "tx_clk";
533 #address-cells = <1>;
534 #size-cells = <0>;
535 #stream-id-cells = <1>;
537 power-domains = <&zynqmp_firmware PD_ETH_1>;
541 compatible = "cdns,zynqmp-gem", "cdns,gem";
543 interrupt-parent = <&gic>;
546 clock-names = "pclk", "hclk", "tx_clk";
547 #address-cells = <1>;
548 #size-cells = <0>;
549 #stream-id-cells = <1>;
551 power-domains = <&zynqmp_firmware PD_ETH_2>;
555 compatible = "cdns,zynqmp-gem", "cdns,gem";
557 interrupt-parent = <&gic>;
560 clock-names = "pclk", "hclk", "tx_clk";
561 #address-cells = <1>;
562 #size-cells = <0>;
563 #stream-id-cells = <1>;
565 power-domains = <&zynqmp_firmware PD_ETH_3>;
569 compatible = "xlnx,zynqmp-gpio-1.0";
571 #address-cells = <0>;
572 #gpio-cells = <0x2>;
573 gpio-controller;
574 interrupt-parent = <&gic>;
576 interrupt-controller;
577 #interrupt-cells = <2>;
579 power-domains = <&zynqmp_firmware PD_GPIO>;
583 compatible = "cdns,i2c-r1p14";
585 interrupt-parent = <&gic>;
588 #address-cells = <1>;
589 #size-cells = <0>;
590 power-domains = <&zynqmp_firmware PD_I2C_0>;
594 compatible = "cdns,i2c-r1p14";
596 interrupt-parent = <&gic>;
599 #address-cells = <1>;
600 #size-cells = <0>;
601 power-domains = <&zynqmp_firmware PD_I2C_1>;
605 compatible = "xlnx,nwl-pcie-2.11";
607 #address-cells = <3>;
608 #size-cells = <2>;
609 #interrupt-cells = <1>;
610 msi-controller;
612 interrupt-parent = <&gic>;
618 interrupt-names = "misc", "dummy", "intx",
620 msi-parent = <&pcie>;
624 reg-names = "breg", "pcireg", "cfg";
625 …ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-pre…
627 bus-range = <0x00 0xff>;
628 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
629 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
633 power-domains = <&zynqmp_firmware PD_PCIE>;
634 pcie_intc: legacy-interrupt-controller {
635 interrupt-controller;
636 #address-cells = <0>;
637 #interrupt-cells = <1>;
641 qspi: spi@ff0f0000 { label
642 compatible = "xlnx,zynqmp-qspi-1.0";
644 clock-names = "ref_clk", "pclk";
646 interrupt-parent = <&gic>;
647 num-cs = <1>;
650 #address-cells = <1>;
651 #size-cells = <0>;
652 #stream-id-cells = <1>;
654 power-domains = <&zynqmp_firmware PD_QSPI>;
658 compatible = "xlnx,zynqmp-psgtr-v1.1";
662 reg-names = "serdes", "siou";
663 #phy-cells = <4>;
667 compatible = "xlnx,zynqmp-rtc";
670 interrupt-parent = <&gic>;
672 interrupt-names = "alarm", "sec";
677 compatible = "ceva,ahci-1v84";
680 interrupt-parent = <&gic>;
682 power-domains = <&zynqmp_firmware PD_SATA>;
683 #stream-id-cells = <4>;
689 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
691 interrupt-parent = <&gic>;
694 clock-names = "clk_xin", "clk_ahb";
695 #stream-id-cells = <1>;
697 #clock-cells = <1>;
698 clock-output-names = "clk_out_sd0", "clk_in_sd0";
699 power-domains = <&zynqmp_firmware PD_SD_0>;
703 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
705 interrupt-parent = <&gic>;
708 clock-names = "clk_xin", "clk_ahb";
709 #stream-id-cells = <1>;
711 #clock-cells = <1>;
712 clock-output-names = "clk_out_sd1", "clk_in_sd1";
713 power-domains = <&zynqmp_firmware PD_SD_1>;
717 compatible = "arm,mmu-500";
719 #iommu-cells = <1>;
721 #global-interrupts = <1>;
722 interrupt-parent = <&gic>;
731 compatible = "cdns,spi-r1p6";
733 interrupt-parent = <&gic>;
736 clock-names = "ref_clk", "pclk";
737 #address-cells = <1>;
738 #size-cells = <0>;
739 power-domains = <&zynqmp_firmware PD_SPI_0>;
743 compatible = "cdns,spi-r1p6";
745 interrupt-parent = <&gic>;
748 clock-names = "ref_clk", "pclk";
749 #address-cells = <1>;
750 #size-cells = <0>;
751 power-domains = <&zynqmp_firmware PD_SPI_1>;
757 interrupt-parent = <&gic>;
760 timer-width = <32>;
761 power-domains = <&zynqmp_firmware PD_TTC_0>;
767 interrupt-parent = <&gic>;
770 timer-width = <32>;
771 power-domains = <&zynqmp_firmware PD_TTC_1>;
777 interrupt-parent = <&gic>;
780 timer-width = <32>;
781 power-domains = <&zynqmp_firmware PD_TTC_2>;
787 interrupt-parent = <&gic>;
790 timer-width = <32>;
791 power-domains = <&zynqmp_firmware PD_TTC_3>;
795 compatible = "cdns,uart-r1p12", "xlnx,xuartps";
797 interrupt-parent = <&gic>;
800 clock-names = "uart_clk", "pclk";
801 power-domains = <&zynqmp_firmware PD_UART_0>;
805 compatible = "cdns,uart-r1p12", "xlnx,xuartps";
807 interrupt-parent = <&gic>;
810 clock-names = "uart_clk", "pclk";
811 power-domains = <&zynqmp_firmware PD_UART_1>;
817 interrupt-parent = <&gic>;
820 clock-names = "clk_xin", "clk_ahb";
821 power-domains = <&zynqmp_firmware PD_USB_0>;
827 interrupt-parent = <&gic>;
830 clock-names = "clk_xin", "clk_ahb";
831 power-domains = <&zynqmp_firmware PD_USB_1>;
835 compatible = "cdns,wdt-r1p2";
837 interrupt-parent = <&gic>;
838 interrupts = <0 113 1>;
840 timeout-sec = <10>;
844 compatible = "cdns,wdt-r1p2";
846 interrupt-parent = <&gic>;
847 interrupts = <0 52 1>;
849 timeout-sec = <10>;
852 zynqmp_dpdma: dma-controller@fd4c0000 {
853 compatible = "xlnx,zynqmp-dpdma";
857 interrupt-parent = <&gic>;
858 clock-names = "axi_clk";
859 power-domains = <&zynqmp_firmware PD_DP>;
860 #dma-cells = <1>;
864 compatible = "xlnx,zynqmp-dpsub-1.7";
870 reg-names = "dp", "blend", "av_buf", "aud";
872 interrupt-parent = <&gic>;
873 clock-names = "dp_apb_clk", "dp_aud_clk",
875 power-domains = <&zynqmp_firmware PD_DP>;
877 dma-names = "vid0", "vid1", "vid2", "gfx0";