Lines Matching +full:zynqmp +full:- +full:qspi +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0
3 * dts file for Xilinx ZynqMP ZCU104
5 * (C) Copyright 2017 - 2020, Xilinx, Inc.
10 /dts-v1/;
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/phy/phy.h>
18 model = "ZynqMP ZCU104 RevC";
19 compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
33 stdout-path = "serial0:115200n8";
42 compatible = "iio-hwmon";
43 io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;
47 compatible = "fixed-clock";
48 #clock-cells = <0>;
49 clock-frequency = <125000000>;
53 compatible = "fixed-clock";
54 #clock-cells = <0>;
55 clock-frequency = <26000000>;
59 compatible = "fixed-clock";
60 #clock-cells = <0>;
61 clock-frequency = <27000000>;
107 phy-handle = <&phy0>;
108 phy-mode = "rgmii-id";
109 phy0: ethernet-phy@c {
111 ti,rx-internal-delay = <0x8>;
112 ti,tx-internal-delay = <0xa>;
113 ti,fifo-depth = <0x1>;
114 ti,dp83867-rxctrl-strap-quirk;
124 clock-frequency = <400000>;
129 gpio-controller;
130 #gpio-cells = <2>;
134 * 0 - IRPS5401_ALERT_B
135 * 1 - HDMI_8T49N241_INT_ALM
136 * 2 - MAX6643_OT_B
137 * 3 - MAX6643_FANFAIL_B
138 * 5 - IIC_MUX_RESET_B
139 * 6 - GEM3_EXP_RESET_B
140 * 7 - FMC_LPC_PRSNT_M2C_B
141 * 4, 10 - 17 - not connected
145 /* Another connection to this bus via PL i2c via PCA9306 - u45 */
146 i2c-mux@74 { /* u34 */
148 #address-cells = <1>;
149 #size-cells = <0>;
152 #address-cells = <1>;
153 #size-cells = <0>;
156 * IIC_EEPROM 1kB memory which uses 256B blocks
158 * 0 - 256B address 0x54
159 * 256B - 512B address 0x55
160 * 512B - 768B address 0x56
161 * 768B - 1024B address 0x57
166 #address-cells = <1>;
167 #size-cells = <1>;
171 i2c@1 {
172 #address-cells = <1>;
173 #size-cells = <0>;
174 reg = <1>;
175 clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
181 #address-cells = <1>;
182 #size-cells = <0>;
184 irps5401_43: irps5401@43 { /* IRPS5401 - u175 */
188 irps5401_44: irps5401@44 { /* IRPS5401 - u180 */
195 #address-cells = <1>;
196 #size-cells = <0>;
200 #io-channel-cells = <1>;
202 shunt-resistor = <5000>;
207 #address-cells = <1>;
208 #size-cells = <0>;
213 #address-cells = <1>;
214 #size-cells = <0>;
222 &qspi {
225 compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
226 #address-cells = <1>;
227 #size-cells = <1>;
240 clock-names = "ref1", "ref2", "ref3";
246 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
247 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
248 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
249 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
250 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
251 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
252 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
253 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
254 phy-names = "sata-phy";
255 phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
261 no-1-8-v;
262 xlnx,mio-bank = <1>;
263 disable-wp;
290 phy-names = "dp-phy0", "dp-phy1";
291 phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
292 <&psgtr 0 PHY_TYPE_DP 1 3>;