Lines Matching +full:io +full:- +full:channel +full:- +full:mux
1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2015 - 2019, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/phy/phy.h>
20 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
35 stdout-path = "serial0:115200n8";
43 gpio-keys {
44 compatible = "gpio-keys";
50 wakeup-source;
56 compatible = "gpio-leds";
57 heartbeat-led {
60 linux,default-trigger = "heartbeat";
64 ina226-u76 {
65 compatible = "iio-hwmon";
66 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
68 ina226-u77 {
69 compatible = "iio-hwmon";
70 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
72 ina226-u78 {
73 compatible = "iio-hwmon";
74 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
76 ina226-u87 {
77 compatible = "iio-hwmon";
78 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
80 ina226-u85 {
81 compatible = "iio-hwmon";
82 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
84 ina226-u86 {
85 compatible = "iio-hwmon";
86 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
88 ina226-u93 {
89 compatible = "iio-hwmon";
90 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
92 ina226-u88 {
93 compatible = "iio-hwmon";
94 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
96 ina226-u15 {
97 compatible = "iio-hwmon";
98 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
100 ina226-u92 {
101 compatible = "iio-hwmon";
102 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
104 ina226-u79 {
105 compatible = "iio-hwmon";
106 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
108 ina226-u81 {
109 compatible = "iio-hwmon";
110 io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
112 ina226-u80 {
113 compatible = "iio-hwmon";
114 io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
116 ina226-u84 {
117 compatible = "iio-hwmon";
118 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
120 ina226-u16 {
121 compatible = "iio-hwmon";
122 io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
124 ina226-u65 {
125 compatible = "iio-hwmon";
126 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
128 ina226-u74 {
129 compatible = "iio-hwmon";
130 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
132 ina226-u75 {
133 compatible = "iio-hwmon";
134 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
139 compatible = "fixed-clock";
140 #clock-cells = <0>;
141 clock-frequency = <48000000>;
145 compatible = "fixed-clock";
146 #clock-cells = <0>;
147 clock-frequency = <114285000>;
193 phy-handle = <&phy0>;
194 phy-mode = "rgmii-id";
195 phy0: ethernet-phy@21 {
197 ti,rx-internal-delay = <0x8>;
198 ti,tx-internal-delay = <0xa>;
199 ti,fifo-depth = <0x1>;
200 ti,dp83867-rxctrl-strap-quirk;
210 clock-frequency = <400000>;
215 gpio-controller; /* IRQ not connected */
216 #gpio-cells = <2>;
217 gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3",
220 gtr-sel0-hog {
221 gpio-hog;
223 output-low; /* PCIE = 0, DP = 1 */
224 line-name = "sel0";
226 gtr-sel1-hog {
227 gpio-hog;
229 output-high; /* PCIE = 0, DP = 1 */
230 line-name = "sel1";
232 gtr-sel2-hog {
233 gpio-hog;
235 output-high; /* PCIE = 0, USB0 = 1 */
236 line-name = "sel2";
238 gtr-sel3-hog {
239 gpio-hog;
241 output-high; /* PCIE = 0, SATA = 1 */
242 line-name = "sel3";
249 gpio-controller; /* IRQ not connected */
250 #gpio-cells = <2>;
251 …gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_…
257 i2c-mux@75 { /* u60 */
259 #address-cells = <1>;
260 #size-cells = <0>;
263 #address-cells = <1>;
264 #size-cells = <0>;
269 #io-channel-cells = <1>;
270 label = "ina226-u76";
272 shunt-resistor = <5000>;
276 #io-channel-cells = <1>;
277 label = "ina226-u77";
279 shunt-resistor = <5000>;
283 #io-channel-cells = <1>;
284 label = "ina226-u78";
286 shunt-resistor = <5000>;
290 #io-channel-cells = <1>;
291 label = "ina226-u87";
293 shunt-resistor = <5000>;
297 #io-channel-cells = <1>;
298 label = "ina226-u85";
300 shunt-resistor = <5000>;
304 #io-channel-cells = <1>;
305 label = "ina226-u86";
307 shunt-resistor = <5000>;
311 #io-channel-cells = <1>;
312 label = "ina226-u93";
314 shunt-resistor = <5000>;
318 #io-channel-cells = <1>;
319 label = "ina226-u88";
321 shunt-resistor = <5000>;
325 #io-channel-cells = <1>;
326 label = "ina226-u15";
328 shunt-resistor = <5000>;
332 #io-channel-cells = <1>;
333 label = "ina226-u92";
335 shunt-resistor = <5000>;
339 #address-cells = <1>;
340 #size-cells = <0>;
345 #io-channel-cells = <1>;
346 label = "ina226-u79";
348 shunt-resistor = <2000>;
352 #io-channel-cells = <1>;
353 label = "ina226-u81";
355 shunt-resistor = <5000>;
359 #io-channel-cells = <1>;
360 label = "ina226-u80";
362 shunt-resistor = <5000>;
366 #io-channel-cells = <1>;
367 label = "ina226-u84";
369 shunt-resistor = <5000>;
373 #io-channel-cells = <1>;
374 label = "ina226-u16";
376 shunt-resistor = <5000>;
380 #io-channel-cells = <1>;
381 label = "ina226-u65";
383 shunt-resistor = <5000>;
387 #io-channel-cells = <1>;
388 label = "ina226-u74";
390 shunt-resistor = <5000>;
394 #io-channel-cells = <1>;
395 label = "ina226-u75";
397 shunt-resistor = <5000>;
401 #address-cells = <1>;
402 #size-cells = <0>;
404 /* MAXIM_PMBUS - 00 */
470 clock-frequency = <400000>;
472 /* PL i2c via PCA9306 - u45 */
473 i2c-mux@74 { /* u34 */
475 #address-cells = <1>;
476 #size-cells = <0>;
479 #address-cells = <1>;
480 #size-cells = <0>;
485 * 0 - 256B address 0x54
486 * 256B - 512B address 0x55
487 * 512B - 768B address 0x56
488 * 768B - 1024B address 0x57
496 #address-cells = <1>;
497 #size-cells = <0>;
499 si5341: clock-generator@36 { /* SI5341 - u69 */
502 #clock-cells = <2>;
503 #address-cells = <1>;
504 #size-cells = <0>;
506 clock-names = "xtal";
507 clock-output-names = "si5341";
510 /* refclk0 for PS-GT, used for DP */
512 always-on;
515 /* refclk2 for PS-GT, used for USB3 */
517 always-on;
520 /* refclk3 for PS-GT, used for SATA */
522 always-on;
525 /* refclk4 for PS-GT, used for PCIE slot */
527 always-on;
530 /* refclk5 for PS-GT, used for PCIE */
532 always-on;
537 always-on;
542 always-on;
547 always-on;
552 #address-cells = <1>;
553 #size-cells = <0>;
555 si570_1: clock-generator@5d { /* USER SI570 - u42 */
556 #clock-cells = <0>;
559 temperature-stability = <50>;
560 factory-fout = <300000000>;
561 clock-frequency = <300000000>;
562 clock-output-names = "si570_user";
566 #address-cells = <1>;
567 #size-cells = <0>;
569 si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
570 #clock-cells = <0>;
573 temperature-stability = <50>; /* copy from zc702 */
574 factory-fout = <156250000>;
575 clock-frequency = <148500000>;
576 clock-output-names = "si570_mgt";
580 #address-cells = <1>;
581 #size-cells = <0>;
583 /* SI5328 - u20 */
585 /* 5 - 7 unconnected */
588 i2c-mux@75 {
590 #address-cells = <1>;
591 #size-cells = <0>;
595 #address-cells = <1>;
596 #size-cells = <0>;
601 #address-cells = <1>;
602 #size-cells = <0>;
607 #address-cells = <1>;
608 #size-cells = <0>;
613 #address-cells = <1>;
614 #size-cells = <0>;
619 #address-cells = <1>;
620 #size-cells = <0>;
625 #address-cells = <1>;
626 #size-cells = <0>;
631 #address-cells = <1>;
632 #size-cells = <0>;
637 #address-cells = <1>;
638 #size-cells = <0>;
653 clock-names = "ref0", "ref1", "ref2", "ref3";
663 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
664 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
665 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
666 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
667 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
668 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
669 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
670 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
671 phy-names = "sata-phy";
678 no-1-8-v;
679 xlnx,mio-bank = <1>;
706 phy-names = "dp-phy0";