Lines Matching +full:mbox +full:- +full:num +full:- +full:users
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/mux/mux.h>
9 #include <dt-bindings/mux/ti-serdes.h>
12 cmn_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
18 cmn_refclk1: clock-cmnrefclk1 {
19 #clock-cells = <0>;
20 compatible = "fixed-clock";
21 clock-frequency = <0>;
27 compatible = "mmio-sram";
29 #address-cells = <1>;
30 #size-cells = <1>;
33 atf-sram@0 {
38 scm_conf: scm-conf@100000 {
39 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
41 #address-cells = <1>;
42 #size-cells = <1>;
46 compatible = "mmio-mux";
48 #mux-control-cells = <1>;
49 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
55 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
63 usb_serdes_mux: mux-controller@4000 {
64 compatible = "mmio-mux";
65 #mux-control-cells = <1>;
66 mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
71 gic500: interrupt-controller@1800000 {
72 compatible = "arm,gic-v3";
73 #address-cells = <2>;
74 #size-cells = <2>;
76 #interrupt-cells = <3>;
77 interrupt-controller;
84 gic_its: msi-controller@1820000 {
85 compatible = "arm,gic-v3-its";
87 socionext,synquacer-pre-its = <0x1000000 0x400000>;
88 msi-controller;
89 #msi-cells = <1>;
93 main_gpio_intr: interrupt-controller@a00000 {
94 compatible = "ti,sci-intr";
96 ti,intr-trigger-type = <1>;
97 interrupt-controller;
98 interrupt-parent = <&gic500>;
99 #interrupt-cells = <1>;
101 ti,sci-dev-id = <131>;
102 ti,interrupt-ranges = <8 392 56>;
106 compatible = "simple-mfd";
107 #address-cells = <2>;
108 #size-cells = <2>;
110 dma-coherent;
111 dma-ranges;
113 ti,sci-dev-id = <199>;
115 main_navss_intr: interrupt-controller@310e0000 {
116 compatible = "ti,sci-intr";
118 ti,intr-trigger-type = <4>;
119 interrupt-controller;
120 interrupt-parent = <&gic500>;
121 #interrupt-cells = <1>;
123 ti,sci-dev-id = <213>;
124 ti,interrupt-ranges = <0 64 64>,
129 main_udmass_inta: interrupt-controller@33d00000 {
130 compatible = "ti,sci-inta";
132 interrupt-controller;
133 interrupt-parent = <&main_navss_intr>;
134 msi-controller;
135 #interrupt-cells = <0>;
137 ti,sci-dev-id = <209>;
138 ti,interrupt-ranges = <0 0 256>;
142 compatible = "ti,am654-secure-proxy";
143 #mbox-cells = <1>;
144 reg-names = "target_data", "rt", "scfg";
148 interrupt-names = "rx_011";
153 compatible = "arm,smmu-v3";
155 interrupt-parent = <&gic500>;
158 interrupt-names = "eventq", "gerror";
159 #iommu-cells = <1>;
163 compatible = "ti,am654-hwspinlock";
165 #hwlock-cells = <1>;
169 compatible = "ti,am654-mailbox";
171 #mbox-cells = <1>;
172 ti,mbox-num-users = <4>;
173 ti,mbox-num-fifos = <16>;
174 interrupt-parent = <&main_navss_intr>;
178 compatible = "ti,am654-mailbox";
180 #mbox-cells = <1>;
181 ti,mbox-num-users = <4>;
182 ti,mbox-num-fifos = <16>;
183 interrupt-parent = <&main_navss_intr>;
187 compatible = "ti,am654-mailbox";
189 #mbox-cells = <1>;
190 ti,mbox-num-users = <4>;
191 ti,mbox-num-fifos = <16>;
192 interrupt-parent = <&main_navss_intr>;
196 compatible = "ti,am654-mailbox";
198 #mbox-cells = <1>;
199 ti,mbox-num-users = <4>;
200 ti,mbox-num-fifos = <16>;
201 interrupt-parent = <&main_navss_intr>;
205 compatible = "ti,am654-mailbox";
207 #mbox-cells = <1>;
208 ti,mbox-num-users = <4>;
209 ti,mbox-num-fifos = <16>;
210 interrupt-parent = <&main_navss_intr>;
214 compatible = "ti,am654-mailbox";
216 #mbox-cells = <1>;
217 ti,mbox-num-users = <4>;
218 ti,mbox-num-fifos = <16>;
219 interrupt-parent = <&main_navss_intr>;
223 compatible = "ti,am654-mailbox";
225 #mbox-cells = <1>;
226 ti,mbox-num-users = <4>;
227 ti,mbox-num-fifos = <16>;
228 interrupt-parent = <&main_navss_intr>;
232 compatible = "ti,am654-mailbox";
234 #mbox-cells = <1>;
235 ti,mbox-num-users = <4>;
236 ti,mbox-num-fifos = <16>;
237 interrupt-parent = <&main_navss_intr>;
241 compatible = "ti,am654-mailbox";
243 #mbox-cells = <1>;
244 ti,mbox-num-users = <4>;
245 ti,mbox-num-fifos = <16>;
246 interrupt-parent = <&main_navss_intr>;
250 compatible = "ti,am654-mailbox";
252 #mbox-cells = <1>;
253 ti,mbox-num-users = <4>;
254 ti,mbox-num-fifos = <16>;
255 interrupt-parent = <&main_navss_intr>;
259 compatible = "ti,am654-mailbox";
261 #mbox-cells = <1>;
262 ti,mbox-num-users = <4>;
263 ti,mbox-num-fifos = <16>;
264 interrupt-parent = <&main_navss_intr>;
268 compatible = "ti,am654-mailbox";
270 #mbox-cells = <1>;
271 ti,mbox-num-users = <4>;
272 ti,mbox-num-fifos = <16>;
273 interrupt-parent = <&main_navss_intr>;
277 compatible = "ti,am654-navss-ringacc";
282 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
283 ti,num-rings = <1024>;
284 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
286 ti,sci-dev-id = <211>;
287 msi-parent = <&main_udmass_inta>;
290 main_udmap: dma-controller@31150000 {
291 compatible = "ti,j721e-navss-main-udmap";
295 reg-names = "gcfg", "rchanrt", "tchanrt";
296 msi-parent = <&main_udmass_inta>;
297 #dma-cells = <1>;
300 ti,sci-dev-id = <212>;
303 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
306 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
309 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
313 compatible = "ti,j721e-cpts";
315 reg-names = "cpts";
317 clock-names = "cpts";
318 interrupts-extended = <&main_navss_intr 391>;
319 interrupt-names = "cpts";
320 ti,cpts-periodic-outputs = <6>;
321 ti,cpts-ext-ts-inputs = <8>;
326 compatible = "ti,j721e-sa2ul";
328 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
329 #address-cells = <2>;
330 #size-cells = <2>;
335 dma-names = "tx", "rx1", "rx2";
336 dma-coherent;
339 compatible = "inside-secure,safexcel-eip76";
347 compatible = "pinctrl-single";
350 #pinctrl-cells = <1>;
351 pinctrl-single,register-width = <32>;
352 pinctrl-single,function-mask = <0xffffffff>;
356 compatible = "ti,j721e-wiz-16g";
357 #address-cells = <1>;
358 #size-cells = <1>;
359 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
361 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
362 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
363 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
364 num-lanes = <2>;
365 #reset-cells = <1>;
368 wiz0_pll0_refclk: pll0-refclk {
370 #clock-cells = <0>;
371 assigned-clocks = <&wiz0_pll0_refclk>;
372 assigned-clock-parents = <&k3_clks 292 11>;
375 wiz0_pll1_refclk: pll1-refclk {
377 #clock-cells = <0>;
378 assigned-clocks = <&wiz0_pll1_refclk>;
379 assigned-clock-parents = <&k3_clks 292 0>;
382 wiz0_refclk_dig: refclk-dig {
384 #clock-cells = <0>;
385 assigned-clocks = <&wiz0_refclk_dig>;
386 assigned-clock-parents = <&k3_clks 292 11>;
389 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
391 #clock-cells = <0>;
394 wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
396 #clock-cells = <0>;
400 compatible = "ti,sierra-phy-t0";
401 reg-names = "serdes";
403 #address-cells = <1>;
404 #size-cells = <0>;
405 #clock-cells = <1>;
407 reset-names = "sierra_reset";
410 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
416 compatible = "ti,j721e-wiz-16g";
417 #address-cells = <1>;
418 #size-cells = <1>;
419 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
421 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
422 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
423 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
424 num-lanes = <2>;
425 #reset-cells = <1>;
428 wiz1_pll0_refclk: pll0-refclk {
430 #clock-cells = <0>;
431 assigned-clocks = <&wiz1_pll0_refclk>;
432 assigned-clock-parents = <&k3_clks 293 13>;
435 wiz1_pll1_refclk: pll1-refclk {
437 #clock-cells = <0>;
438 assigned-clocks = <&wiz1_pll1_refclk>;
439 assigned-clock-parents = <&k3_clks 293 0>;
442 wiz1_refclk_dig: refclk-dig {
444 #clock-cells = <0>;
445 assigned-clocks = <&wiz1_refclk_dig>;
446 assigned-clock-parents = <&k3_clks 293 13>;
449 wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{
451 #clock-cells = <0>;
454 wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
456 #clock-cells = <0>;
460 compatible = "ti,sierra-phy-t0";
461 reg-names = "serdes";
463 #address-cells = <1>;
464 #size-cells = <0>;
465 #clock-cells = <1>;
467 reset-names = "sierra_reset";
470 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
476 compatible = "ti,j721e-wiz-16g";
477 #address-cells = <1>;
478 #size-cells = <1>;
479 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
481 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
482 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
483 assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
484 num-lanes = <2>;
485 #reset-cells = <1>;
488 wiz2_pll0_refclk: pll0-refclk {
490 #clock-cells = <0>;
491 assigned-clocks = <&wiz2_pll0_refclk>;
492 assigned-clock-parents = <&k3_clks 294 11>;
495 wiz2_pll1_refclk: pll1-refclk {
497 #clock-cells = <0>;
498 assigned-clocks = <&wiz2_pll1_refclk>;
499 assigned-clock-parents = <&k3_clks 294 0>;
502 wiz2_refclk_dig: refclk-dig {
504 #clock-cells = <0>;
505 assigned-clocks = <&wiz2_refclk_dig>;
506 assigned-clock-parents = <&k3_clks 294 11>;
509 wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div {
511 #clock-cells = <0>;
514 wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
516 #clock-cells = <0>;
520 compatible = "ti,sierra-phy-t0";
521 reg-names = "serdes";
523 #address-cells = <1>;
524 #size-cells = <0>;
525 #clock-cells = <1>;
527 reset-names = "sierra_reset";
530 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
536 compatible = "ti,j721e-wiz-16g";
537 #address-cells = <1>;
538 #size-cells = <1>;
539 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
541 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
542 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
543 assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
544 num-lanes = <2>;
545 #reset-cells = <1>;
548 wiz3_pll0_refclk: pll0-refclk {
550 #clock-cells = <0>;
551 assigned-clocks = <&wiz3_pll0_refclk>;
552 assigned-clock-parents = <&k3_clks 295 9>;
555 wiz3_pll1_refclk: pll1-refclk {
557 #clock-cells = <0>;
558 assigned-clocks = <&wiz3_pll1_refclk>;
559 assigned-clock-parents = <&k3_clks 295 0>;
562 wiz3_refclk_dig: refclk-dig {
564 #clock-cells = <0>;
565 assigned-clocks = <&wiz3_refclk_dig>;
566 assigned-clock-parents = <&k3_clks 295 9>;
569 wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div {
571 #clock-cells = <0>;
574 wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
576 #clock-cells = <0>;
580 compatible = "ti,sierra-phy-t0";
581 reg-names = "serdes";
583 #address-cells = <1>;
584 #size-cells = <0>;
585 #clock-cells = <1>;
587 reset-names = "sierra_reset";
590 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
596 compatible = "ti,j721e-pcie-host";
601 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
602 interrupt-names = "link_state";
605 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
606 max-link-speed = <3>;
607 num-lanes = <2>;
608 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
610 clock-names = "fck";
611 #address-cells = <3>;
612 #size-cells = <2>;
613 bus-range = <0x0 0xf>;
614 vendor-id = <0x104c>;
615 device-id = <0xb00d>;
616 msi-map = <0x0 &gic_its 0x0 0x10000>;
617 dma-coherent;
620 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
623 pcie0_ep: pcie-ep@2900000 {
624 compatible = "ti,j721e-pcie-ep";
629 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
630 interrupt-names = "link_state";
632 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
633 max-link-speed = <3>;
634 num-lanes = <2>;
635 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
637 clock-names = "fck";
638 max-functions = /bits/ 8 <6>;
639 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
640 dma-coherent;
644 compatible = "ti,j721e-pcie-host";
649 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
650 interrupt-names = "link_state";
653 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
654 max-link-speed = <3>;
655 num-lanes = <2>;
656 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
658 clock-names = "fck";
659 #address-cells = <3>;
660 #size-cells = <2>;
661 bus-range = <0x0 0xf>;
662 vendor-id = <0x104c>;
663 device-id = <0xb00d>;
664 msi-map = <0x0 &gic_its 0x10000 0x10000>;
665 dma-coherent;
668 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
671 pcie1_ep: pcie-ep@2910000 {
672 compatible = "ti,j721e-pcie-ep";
677 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
678 interrupt-names = "link_state";
680 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
681 max-link-speed = <3>;
682 num-lanes = <2>;
683 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
685 clock-names = "fck";
686 max-functions = /bits/ 8 <6>;
687 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
688 dma-coherent;
692 compatible = "ti,j721e-pcie-host";
697 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
698 interrupt-names = "link_state";
701 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
702 max-link-speed = <3>;
703 num-lanes = <2>;
704 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
706 clock-names = "fck";
707 #address-cells = <3>;
708 #size-cells = <2>;
709 bus-range = <0x0 0xf>;
710 vendor-id = <0x104c>;
711 device-id = <0xb00d>;
712 msi-map = <0x0 &gic_its 0x20000 0x10000>;
713 dma-coherent;
716 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
719 pcie2_ep: pcie-ep@2920000 {
720 compatible = "ti,j721e-pcie-ep";
725 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
726 interrupt-names = "link_state";
728 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
729 max-link-speed = <3>;
730 num-lanes = <2>;
731 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
733 clock-names = "fck";
734 max-functions = /bits/ 8 <6>;
735 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
736 dma-coherent;
740 compatible = "ti,j721e-pcie-host";
745 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
746 interrupt-names = "link_state";
749 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
750 max-link-speed = <3>;
751 num-lanes = <2>;
752 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
754 clock-names = "fck";
755 #address-cells = <3>;
756 #size-cells = <2>;
757 bus-range = <0x0 0xf>;
758 vendor-id = <0x104c>;
759 device-id = <0xb00d>;
760 msi-map = <0x0 &gic_its 0x30000 0x10000>;
761 dma-coherent;
764 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
767 pcie3_ep: pcie-ep@2930000 {
768 compatible = "ti,j721e-pcie-ep";
773 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
774 interrupt-names = "link_state";
776 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
777 max-link-speed = <3>;
778 num-lanes = <2>;
779 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
781 clock-names = "fck";
782 max-functions = /bits/ 8 <6>;
783 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
784 dma-coherent;
785 #address-cells = <2>;
786 #size-cells = <2>;
790 compatible = "ti,j721e-uart", "ti,am654-uart";
793 clock-frequency = <48000000>;
794 current-speed = <115200>;
795 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
797 clock-names = "fclk";
801 compatible = "ti,j721e-uart", "ti,am654-uart";
804 clock-frequency = <48000000>;
805 current-speed = <115200>;
806 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
808 clock-names = "fclk";
812 compatible = "ti,j721e-uart", "ti,am654-uart";
815 clock-frequency = <48000000>;
816 current-speed = <115200>;
817 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
819 clock-names = "fclk";
823 compatible = "ti,j721e-uart", "ti,am654-uart";
826 clock-frequency = <48000000>;
827 current-speed = <115200>;
828 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
830 clock-names = "fclk";
834 compatible = "ti,j721e-uart", "ti,am654-uart";
837 clock-frequency = <48000000>;
838 current-speed = <115200>;
839 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
841 clock-names = "fclk";
845 compatible = "ti,j721e-uart", "ti,am654-uart";
848 clock-frequency = <48000000>;
849 current-speed = <115200>;
850 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
852 clock-names = "fclk";
856 compatible = "ti,j721e-uart", "ti,am654-uart";
859 clock-frequency = <48000000>;
860 current-speed = <115200>;
861 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
863 clock-names = "fclk";
867 compatible = "ti,j721e-uart", "ti,am654-uart";
870 clock-frequency = <48000000>;
871 current-speed = <115200>;
872 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
874 clock-names = "fclk";
878 compatible = "ti,j721e-uart", "ti,am654-uart";
881 clock-frequency = <48000000>;
882 current-speed = <115200>;
883 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
885 clock-names = "fclk";
889 compatible = "ti,j721e-uart", "ti,am654-uart";
892 clock-frequency = <48000000>;
893 current-speed = <115200>;
894 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
896 clock-names = "fclk";
900 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
902 gpio-controller;
903 #gpio-cells = <2>;
904 interrupt-parent = <&main_gpio_intr>;
907 interrupt-controller;
908 #interrupt-cells = <2>;
910 ti,davinci-gpio-unbanked = <0>;
911 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
913 clock-names = "gpio";
917 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
919 gpio-controller;
920 #gpio-cells = <2>;
921 interrupt-parent = <&main_gpio_intr>;
923 interrupt-controller;
924 #interrupt-cells = <2>;
926 ti,davinci-gpio-unbanked = <0>;
927 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
929 clock-names = "gpio";
933 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
935 gpio-controller;
936 #gpio-cells = <2>;
937 interrupt-parent = <&main_gpio_intr>;
940 interrupt-controller;
941 #interrupt-cells = <2>;
943 ti,davinci-gpio-unbanked = <0>;
944 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
946 clock-names = "gpio";
950 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
952 gpio-controller;
953 #gpio-cells = <2>;
954 interrupt-parent = <&main_gpio_intr>;
956 interrupt-controller;
957 #interrupt-cells = <2>;
959 ti,davinci-gpio-unbanked = <0>;
960 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
962 clock-names = "gpio";
966 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
968 gpio-controller;
969 #gpio-cells = <2>;
970 interrupt-parent = <&main_gpio_intr>;
973 interrupt-controller;
974 #interrupt-cells = <2>;
976 ti,davinci-gpio-unbanked = <0>;
977 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
979 clock-names = "gpio";
983 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
985 gpio-controller;
986 #gpio-cells = <2>;
987 interrupt-parent = <&main_gpio_intr>;
989 interrupt-controller;
990 #interrupt-cells = <2>;
992 ti,davinci-gpio-unbanked = <0>;
993 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
995 clock-names = "gpio";
999 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1001 gpio-controller;
1002 #gpio-cells = <2>;
1003 interrupt-parent = <&main_gpio_intr>;
1006 interrupt-controller;
1007 #interrupt-cells = <2>;
1009 ti,davinci-gpio-unbanked = <0>;
1010 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
1012 clock-names = "gpio";
1016 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1018 gpio-controller;
1019 #gpio-cells = <2>;
1020 interrupt-parent = <&main_gpio_intr>;
1022 interrupt-controller;
1023 #interrupt-cells = <2>;
1025 ti,davinci-gpio-unbanked = <0>;
1026 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
1028 clock-names = "gpio";
1032 compatible = "ti,j721e-sdhci-8bit";
1035 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
1036 clock-names = "clk_ahb", "clk_xin";
1038 assigned-clocks = <&k3_clks 91 1>;
1039 assigned-clock-parents = <&k3_clks 91 2>;
1040 bus-width = <8>;
1041 mmc-hs200-1_8v;
1042 mmc-ddr-1_8v;
1043 ti,otap-del-sel-legacy = <0xf>;
1044 ti,otap-del-sel-mmc-hs = <0xf>;
1045 ti,otap-del-sel-ddr52 = <0x5>;
1046 ti,otap-del-sel-hs200 = <0x6>;
1047 ti,otap-del-sel-hs400 = <0x0>;
1048 ti,itap-del-sel-legacy = <0x10>;
1049 ti,itap-del-sel-mmc-hs = <0xa>;
1050 ti,itap-del-sel-ddr52 = <0x3>;
1051 ti,trm-icp = <0x8>;
1052 ti,strobe-sel = <0x77>;
1053 dma-coherent;
1057 compatible = "ti,j721e-sdhci-4bit";
1060 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
1061 clock-names = "clk_ahb", "clk_xin";
1063 assigned-clocks = <&k3_clks 92 0>;
1064 assigned-clock-parents = <&k3_clks 92 1>;
1065 ti,otap-del-sel-legacy = <0x0>;
1066 ti,otap-del-sel-sd-hs = <0xf>;
1067 ti,otap-del-sel-sdr12 = <0xf>;
1068 ti,otap-del-sel-sdr25 = <0xf>;
1069 ti,otap-del-sel-sdr50 = <0xc>;
1070 ti,otap-del-sel-ddr50 = <0xc>;
1071 ti,itap-del-sel-legacy = <0x0>;
1072 ti,itap-del-sel-sd-hs = <0x0>;
1073 ti,itap-del-sel-sdr12 = <0x0>;
1074 ti,itap-del-sel-sdr25 = <0x0>;
1075 ti,itap-del-sel-ddr50 = <0x2>;
1076 ti,trm-icp = <0x8>;
1077 ti,clkbuf-sel = <0x7>;
1078 dma-coherent;
1079 sdhci-caps-mask = <0x2 0x0>;
1083 compatible = "ti,j721e-sdhci-4bit";
1086 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
1087 clock-names = "clk_ahb", "clk_xin";
1089 assigned-clocks = <&k3_clks 93 0>;
1090 assigned-clock-parents = <&k3_clks 93 1>;
1091 ti,otap-del-sel-legacy = <0x0>;
1092 ti,otap-del-sel-sd-hs = <0xf>;
1093 ti,otap-del-sel-sdr12 = <0xf>;
1094 ti,otap-del-sel-sdr25 = <0xf>;
1095 ti,otap-del-sel-sdr50 = <0xc>;
1096 ti,otap-del-sel-ddr50 = <0xc>;
1097 ti,itap-del-sel-legacy = <0x0>;
1098 ti,itap-del-sel-sd-hs = <0x0>;
1099 ti,itap-del-sel-sdr12 = <0x0>;
1100 ti,itap-del-sel-sdr25 = <0x0>;
1101 ti,itap-del-sel-ddr50 = <0x2>;
1102 ti,trm-icp = <0x8>;
1103 ti,clkbuf-sel = <0x7>;
1104 dma-coherent;
1105 sdhci-caps-mask = <0x2 0x0>;
1108 usbss0: cdns-usb@4104000 {
1109 compatible = "ti,j721e-usb";
1111 dma-coherent;
1112 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
1114 clock-names = "ref", "lpm";
1115 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */
1116 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
1117 #address-cells = <2>;
1118 #size-cells = <2>;
1126 reg-names = "otg", "xhci", "dev";
1130 interrupt-names = "host",
1133 maximum-speed = "super-speed";
1138 usbss1: cdns-usb@4114000 {
1139 compatible = "ti,j721e-usb";
1141 dma-coherent;
1142 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
1144 clock-names = "ref", "lpm";
1145 assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */
1146 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
1147 #address-cells = <2>;
1148 #size-cells = <2>;
1156 reg-names = "otg", "xhci", "dev";
1160 interrupt-names = "host",
1163 maximum-speed = "super-speed";
1169 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1172 #address-cells = <1>;
1173 #size-cells = <0>;
1174 clock-names = "fck";
1176 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
1180 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1183 #address-cells = <1>;
1184 #size-cells = <0>;
1185 clock-names = "fck";
1187 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
1191 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1194 #address-cells = <1>;
1195 #size-cells = <0>;
1196 clock-names = "fck";
1198 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
1202 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1205 #address-cells = <1>;
1206 #size-cells = <0>;
1207 clock-names = "fck";
1209 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
1213 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1216 #address-cells = <1>;
1217 #size-cells = <0>;
1218 clock-names = "fck";
1220 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
1224 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1227 #address-cells = <1>;
1228 #size-cells = <0>;
1229 clock-names = "fck";
1231 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
1235 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1238 #address-cells = <1>;
1239 #size-cells = <0>;
1240 clock-names = "fck";
1242 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
1245 ufs_wrapper: ufs-wrapper@4e80000 {
1246 compatible = "ti,j721e-ufs";
1248 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
1250 assigned-clocks = <&k3_clks 277 1>;
1251 assigned-clock-parents = <&k3_clks 277 4>;
1253 #address-cells = <2>;
1254 #size-cells = <2>;
1257 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
1260 freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>;
1262 clock-names = "core_clk", "phy_clk", "ref_clk";
1263 dma-coherent;
1268 compatible = "ti,j721e-dss";
1291 reg-names = "common_m", "common_s0",
1303 clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
1305 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
1311 interrupt-names = "common_m",
1317 #address-cells = <1>;
1318 #size-cells = <0>;
1323 compatible = "ti,am33xx-mcasp-audio";
1326 reg-names = "mpu","dat";
1329 interrupt-names = "tx", "rx";
1332 dma-names = "tx", "rx";
1335 clock-names = "fck";
1336 power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>;
1340 compatible = "ti,am33xx-mcasp-audio";
1343 reg-names = "mpu","dat";
1346 interrupt-names = "tx", "rx";
1349 dma-names = "tx", "rx";
1352 clock-names = "fck";
1353 power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>;
1357 compatible = "ti,am33xx-mcasp-audio";
1360 reg-names = "mpu","dat";
1363 interrupt-names = "tx", "rx";
1366 dma-names = "tx", "rx";
1369 clock-names = "fck";
1370 power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>;
1374 compatible = "ti,am33xx-mcasp-audio";
1377 reg-names = "mpu","dat";
1380 interrupt-names = "tx", "rx";
1383 dma-names = "tx", "rx";
1386 clock-names = "fck";
1387 power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>;
1391 compatible = "ti,am33xx-mcasp-audio";
1394 reg-names = "mpu","dat";
1397 interrupt-names = "tx", "rx";
1400 dma-names = "tx", "rx";
1403 clock-names = "fck";
1404 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
1408 compatible = "ti,am33xx-mcasp-audio";
1411 reg-names = "mpu","dat";
1414 interrupt-names = "tx", "rx";
1417 dma-names = "tx", "rx";
1420 clock-names = "fck";
1421 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
1425 compatible = "ti,am33xx-mcasp-audio";
1428 reg-names = "mpu","dat";
1431 interrupt-names = "tx", "rx";
1434 dma-names = "tx", "rx";
1437 clock-names = "fck";
1438 power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>;
1442 compatible = "ti,am33xx-mcasp-audio";
1445 reg-names = "mpu","dat";
1448 interrupt-names = "tx", "rx";
1451 dma-names = "tx", "rx";
1454 clock-names = "fck";
1455 power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>;
1459 compatible = "ti,am33xx-mcasp-audio";
1462 reg-names = "mpu","dat";
1465 interrupt-names = "tx", "rx";
1468 dma-names = "tx", "rx";
1471 clock-names = "fck";
1472 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
1476 compatible = "ti,am33xx-mcasp-audio";
1479 reg-names = "mpu","dat";
1482 interrupt-names = "tx", "rx";
1485 dma-names = "tx", "rx";
1488 clock-names = "fck";
1489 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
1493 compatible = "ti,am33xx-mcasp-audio";
1496 reg-names = "mpu","dat";
1499 interrupt-names = "tx", "rx";
1502 dma-names = "tx", "rx";
1505 clock-names = "fck";
1506 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
1510 compatible = "ti,am33xx-mcasp-audio";
1513 reg-names = "mpu","dat";
1516 interrupt-names = "tx", "rx";
1519 dma-names = "tx", "rx";
1522 clock-names = "fck";
1523 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
1527 compatible = "ti,j7-rti-wdt";
1530 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
1531 assigned-clocks = <&k3_clks 252 1>;
1532 assigned-clock-parents = <&k3_clks 252 5>;
1536 compatible = "ti,j7-rti-wdt";
1539 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
1540 assigned-clocks = <&k3_clks 253 1>;
1541 assigned-clock-parents = <&k3_clks 253 5>;
1545 compatible = "ti,j721e-r5fss";
1546 ti,cluster-mode = <1>;
1547 #address-cells = <1>;
1548 #size-cells = <1>;
1551 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
1554 compatible = "ti,j721e-r5f";
1557 reg-names = "atcm", "btcm";
1559 ti,sci-dev-id = <245>;
1560 ti,sci-proc-ids = <0x06 0xff>;
1562 firmware-name = "j7-main-r5f0_0-fw";
1563 ti,atcm-enable = <1>;
1564 ti,btcm-enable = <1>;
1569 compatible = "ti,j721e-r5f";
1572 reg-names = "atcm", "btcm";
1574 ti,sci-dev-id = <246>;
1575 ti,sci-proc-ids = <0x07 0xff>;
1577 firmware-name = "j7-main-r5f0_1-fw";
1578 ti,atcm-enable = <1>;
1579 ti,btcm-enable = <1>;
1585 compatible = "ti,j721e-r5fss";
1586 ti,cluster-mode = <1>;
1587 #address-cells = <1>;
1588 #size-cells = <1>;
1591 power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>;
1594 compatible = "ti,j721e-r5f";
1597 reg-names = "atcm", "btcm";
1599 ti,sci-dev-id = <247>;
1600 ti,sci-proc-ids = <0x08 0xff>;
1602 firmware-name = "j7-main-r5f1_0-fw";
1603 ti,atcm-enable = <1>;
1604 ti,btcm-enable = <1>;
1609 compatible = "ti,j721e-r5f";
1612 reg-names = "atcm", "btcm";
1614 ti,sci-dev-id = <248>;
1615 ti,sci-proc-ids = <0x09 0xff>;
1617 firmware-name = "j7-main-r5f1_1-fw";
1618 ti,atcm-enable = <1>;
1619 ti,btcm-enable = <1>;
1625 compatible = "ti,j721e-c66-dsp";
1629 reg-names = "l2sram", "l1pram", "l1dram";
1631 ti,sci-dev-id = <142>;
1632 ti,sci-proc-ids = <0x03 0xff>;
1634 firmware-name = "j7-c66_0-fw";
1638 compatible = "ti,j721e-c66-dsp";
1642 reg-names = "l2sram", "l1pram", "l1dram";
1644 ti,sci-dev-id = <143>;
1645 ti,sci-proc-ids = <0x04 0xff>;
1647 firmware-name = "j7-c66_1-fw";
1651 compatible = "ti,j721e-c71-dsp";
1654 reg-names = "l2sram", "l1dram";
1656 ti,sci-dev-id = <15>;
1657 ti,sci-proc-ids = <0x30 0xff>;
1659 firmware-name = "j7-c71_0-fw";
1663 compatible = "ti,j721e-icssg";
1665 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
1666 #address-cells = <1>;
1667 #size-cells = <1>;
1674 reg-names = "dram0", "dram1",
1679 compatible = "ti,pruss-cfg", "syscon";
1681 #address-cells = <1>;
1682 #size-cells = <1>;
1686 #address-cells = <1>;
1687 #size-cells = <0>;
1689 icssg0_coreclk_mux: coreclk-mux@3c {
1691 #clock-cells = <0>;
1694 assigned-clocks = <&icssg0_coreclk_mux>;
1695 assigned-clock-parents = <&k3_clks 119 1>;
1698 icssg0_iepclk_mux: iepclk-mux@30 {
1700 #clock-cells = <0>;
1703 assigned-clocks = <&icssg0_iepclk_mux>;
1704 assigned-clock-parents = <&icssg0_coreclk_mux>;
1709 icssg0_mii_rt: mii-rt@32000 {
1710 compatible = "ti,pruss-mii", "syscon";
1714 icssg0_mii_g_rt: mii-g-rt@33000 {
1715 compatible = "ti,pruss-mii-g", "syscon";
1719 icssg0_intc: interrupt-controller@20000 {
1720 compatible = "ti,icssg-intc";
1722 interrupt-controller;
1723 #interrupt-cells = <3>;
1732 interrupt-names = "host_intr0", "host_intr1",
1739 compatible = "ti,j721e-pru";
1743 reg-names = "iram", "control", "debug";
1744 firmware-name = "j7-pru0_0-fw";
1748 compatible = "ti,j721e-rtu";
1752 reg-names = "iram", "control", "debug";
1753 firmware-name = "j7-rtu0_0-fw";
1757 compatible = "ti,j721e-tx-pru";
1761 reg-names = "iram", "control", "debug";
1762 firmware-name = "j7-txpru0_0-fw";
1766 compatible = "ti,j721e-pru";
1770 reg-names = "iram", "control", "debug";
1771 firmware-name = "j7-pru0_1-fw";
1775 compatible = "ti,j721e-rtu";
1779 reg-names = "iram", "control", "debug";
1780 firmware-name = "j7-rtu0_1-fw";
1784 compatible = "ti,j721e-tx-pru";
1788 reg-names = "iram", "control", "debug";
1789 firmware-name = "j7-txpru0_1-fw";
1796 clock-names = "fck";
1797 #address-cells = <1>;
1798 #size-cells = <0>;
1804 compatible = "ti,j721e-icssg";
1806 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
1807 #address-cells = <1>;
1808 #size-cells = <1>;
1815 reg-names = "dram0", "dram1",
1820 compatible = "ti,pruss-cfg", "syscon";
1822 #address-cells = <1>;
1823 #size-cells = <1>;
1827 #address-cells = <1>;
1828 #size-cells = <0>;
1830 icssg1_coreclk_mux: coreclk-mux@3c {
1832 #clock-cells = <0>;
1835 assigned-clocks = <&icssg1_coreclk_mux>;
1836 assigned-clock-parents = <&k3_clks 120 4>;
1839 icssg1_iepclk_mux: iepclk-mux@30 {
1841 #clock-cells = <0>;
1844 assigned-clocks = <&icssg1_iepclk_mux>;
1845 assigned-clock-parents = <&icssg1_coreclk_mux>;
1850 icssg1_mii_rt: mii-rt@32000 {
1851 compatible = "ti,pruss-mii", "syscon";
1855 icssg1_mii_g_rt: mii-g-rt@33000 {
1856 compatible = "ti,pruss-mii-g", "syscon";
1860 icssg1_intc: interrupt-controller@20000 {
1861 compatible = "ti,icssg-intc";
1863 interrupt-controller;
1864 #interrupt-cells = <3>;
1873 interrupt-names = "host_intr0", "host_intr1",
1880 compatible = "ti,j721e-pru";
1884 reg-names = "iram", "control", "debug";
1885 firmware-name = "j7-pru1_0-fw";
1889 compatible = "ti,j721e-rtu";
1893 reg-names = "iram", "control", "debug";
1894 firmware-name = "j7-rtu1_0-fw";
1898 compatible = "ti,j721e-tx-pru";
1902 reg-names = "iram", "control", "debug";
1903 firmware-name = "j7-txpru1_0-fw";
1907 compatible = "ti,j721e-pru";
1911 reg-names = "iram", "control", "debug";
1912 firmware-name = "j7-pru1_1-fw";
1916 compatible = "ti,j721e-rtu";
1920 reg-names = "iram", "control", "debug";
1921 firmware-name = "j7-rtu1_1-fw";
1925 compatible = "ti,j721e-tx-pru";
1929 reg-names = "iram", "control", "debug";
1930 firmware-name = "j7-txpru1_1-fw";
1937 clock-names = "fck";
1938 #address-cells = <1>;
1939 #size-cells = <0>;