Lines Matching +full:j721e +full:- +full:system +full:- +full:controller
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
8 #include "k3-j721e-som-p0.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/phy/phy-cadence.h>
16 stdout-path = "serial2:115200n8";
20 gpio_keys: gpio-keys {
21 compatible = "gpio-keys";
23 pinctrl-names = "default";
24 pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>;
39 evm_12v0: fixedregulator-evm12v0 {
41 compatible = "regulator-fixed";
42 regulator-name = "evm_12v0";
43 regulator-min-microvolt = <12000000>;
44 regulator-max-microvolt = <12000000>;
45 regulator-always-on;
46 regulator-boot-on;
49 vsys_3v3: fixedregulator-vsys3v3 {
51 compatible = "regulator-fixed";
52 regulator-name = "vsys_3v3";
53 regulator-min-microvolt = <3300000>;
54 regulator-max-microvolt = <3300000>;
55 vin-supply = <&evm_12v0>;
56 regulator-always-on;
57 regulator-boot-on;
60 vsys_5v0: fixedregulator-vsys5v0 {
62 compatible = "regulator-fixed";
63 regulator-name = "vsys_5v0";
64 regulator-min-microvolt = <5000000>;
65 regulator-max-microvolt = <5000000>;
66 vin-supply = <&evm_12v0>;
67 regulator-always-on;
68 regulator-boot-on;
71 vdd_mmc1: fixedregulator-sd {
72 compatible = "regulator-fixed";
73 regulator-name = "vdd_mmc1";
74 regulator-min-microvolt = <3300000>;
75 regulator-max-microvolt = <3300000>;
76 regulator-boot-on;
77 enable-active-high;
78 vin-supply = <&vsys_3v3>;
82 vdd_sd_dv_alt: gpio-regulator-TLV71033 {
83 compatible = "regulator-gpio";
84 pinctrl-names = "default";
85 pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
86 regulator-name = "tlv71033";
87 regulator-min-microvolt = <1800000>;
88 regulator-max-microvolt = <3300000>;
89 regulator-boot-on;
90 vin-supply = <&vsys_5v0>;
97 compatible = "ti,j721e-cpb-audio";
98 model = "j721e-cpb";
100 ti,cpb-mcasp = <&mcasp10>;
101 ti,cpb-codec = <&pcm3168a_1>;
107 clock-names = "cpb-mcasp-auxclk",
108 "cpb-mcasp-auxclk-48000", "cpb-mcasp-auxclk-44100",
109 "cpb-codec-scki",
110 "cpb-codec-scki-48000", "cpb-codec-scki-44100";
115 sw10_button_pins_default: sw10-button-pins-default {
116 pinctrl-single,pins = <
121 main_mmc1_pins_default: main-mmc1-pins-default {
122 pinctrl-single,pins = <
135 vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default {
136 pinctrl-single,pins = <
141 main_usbss0_pins_default: main-usbss0-pins-default {
142 pinctrl-single,pins = <
148 main_usbss1_pins_default: main-usbss1-pins-default {
149 pinctrl-single,pins = <
154 main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default {
155 pinctrl-single,pins = <
160 main_i2c0_pins_default: main-i2c0-pins-default {
161 pinctrl-single,pins = <
167 main_i2c1_pins_default: main-i2c1-pins-default {
168 pinctrl-single,pins = <
174 main_i2c3_pins_default: main-i2c3-pins-default {
175 pinctrl-single,pins = <
181 main_i2c6_pins_default: main-i2c6-pins-default {
182 pinctrl-single,pins = <
188 mcasp10_pins_default: mcasp10-pins-default {
189 pinctrl-single,pins = <
202 audi_ext_refclk2_pins_default: audi-ext-refclk2-pins-default {
203 pinctrl-single,pins = <
210 sw11_button_pins_default: sw11-button-pins-default {
211 pinctrl-single,pins = <
216 mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
217 pinctrl-single,pins = <
229 mcu_cpsw_pins_default: mcu-cpsw-pins-default {
230 pinctrl-single,pins = <
246 mcu_mdio_pins_default: mcu-mdio1-pins-default {
247 pinctrl-single,pins = <
255 /* Wakeup UART is used by System firmware */
260 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
323 non-removable;
324 ti,driver-strength-ohm = <50>;
325 disable-wp;
330 vmmc-supply = <&vdd_mmc1>;
331 vqmmc-supply = <&vdd_sd_dv_alt>;
332 pinctrl-names = "default";
333 pinctrl-0 = <&main_mmc1_pins_default>;
334 ti,driver-strength-ohm = <50>;
335 disable-wp;
344 idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */
348 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
357 typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
358 typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */
364 cdns,num-lanes = <2>;
365 #phy-cells = <0>;
366 cdns,phy-type = <PHY_TYPE_USB3>;
372 pinctrl-names = "default";
373 pinctrl-0 = <&main_usbss0_pins_default>;
374 ti,vbus-divider;
379 maximum-speed = "super-speed";
381 phy-names = "cdns3,usb3-phy";
385 pinctrl-names = "default";
386 pinctrl-0 = <&main_usbss1_pins_default>;
387 ti,usb2-only;
392 maximum-speed = "high-speed";
396 pinctrl-names = "default";
397 pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
400 compatible = "jedec,spi-nor";
402 spi-tx-bus-width = <1>;
403 spi-rx-bus-width = <4>;
404 spi-max-frequency = <40000000>;
405 cdns,tshsl-ns = <60>;
406 cdns,tsd2d-ns = <60>;
407 cdns,tchsh-ns = <60>;
408 cdns,tslch-ns = <60>;
409 cdns,read-delay = <2>;
410 #address-cells = <1>;
411 #size-cells = <1>;
417 ti,adc-channels = <0 1 2 3 4 5 6 7>;
423 ti,adc-channels = <0 1 2 3 4 5 6 7>;
428 pinctrl-names = "default";
429 pinctrl-0 = <&main_i2c0_pins_default>;
430 clock-frequency = <400000>;
435 gpio-controller;
436 #gpio-cells = <2>;
442 gpio-controller;
443 #gpio-cells = <2>;
445 p09-hog {
446 /* P11 - MCASP/TRACE_MUX_S0 */
447 gpio-hog;
449 output-low;
450 line-name = "MCASP/TRACE_MUX_S0";
453 p10-hog {
454 /* P12 - MCASP/TRACE_MUX_S1 */
455 gpio-hog;
457 output-high;
458 line-name = "MCASP/TRACE_MUX_S1";
464 pinctrl-names = "default";
465 pinctrl-0 = <&main_i2c1_pins_default>;
466 clock-frequency = <400000>;
471 gpio-controller;
472 #gpio-cells = <2>;
473 pinctrl-names = "default";
474 pinctrl-0 = <&main_i2c1_exp4_pins_default>;
475 interrupt-parent = <&main_gpio1>;
477 interrupt-controller;
478 #interrupt-cells = <2>;
484 pinctrl-names = "default";
485 pinctrl-0 = <&audi_ext_refclk2_pins_default>;
489 pinctrl-names = "default";
490 pinctrl-0 = <&main_i2c3_pins_default>;
491 clock-frequency = <400000>;
496 gpio-controller;
497 #gpio-cells = <2>;
500 pcm3168a_1: audio-codec@44 {
504 #sound-dai-cells = <1>;
506 reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>;
508 /* C_AUDIO_REFCLK2 -> RGMII6_RXC (W26) */
510 clock-names = "scki";
512 /* HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK -> REFCLK2 */
513 assigned-clocks = <&k3_clks 157 371>;
514 assigned-clock-parents = <&k3_clks 157 400>;
515 assigned-clock-rates = <24576000>; /* for 48KHz */
517 VDD1-supply = <&vsys_3v3>;
518 VDD2-supply = <&vsys_3v3>;
519 VCCAD1-supply = <&vsys_5v0>;
520 VCCAD2-supply = <&vsys_5v0>;
521 VCCDA1-supply = <&vsys_5v0>;
522 VCCDA2-supply = <&vsys_5v0>;
527 pinctrl-names = "default";
528 pinctrl-0 = <&main_i2c6_pins_default>;
529 clock-frequency = <400000>;
534 gpio-controller;
535 #gpio-cells = <2>;
540 pinctrl-names = "default";
541 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
545 phy0: ethernet-phy@0 {
547 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
548 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
553 phy-mode = "rgmii-rxid";
554 phy-handle = <&phy0>;
561 * VP0 - DisplayPort SST
562 * VP1 - DPI0
563 * VP2 - DSI
564 * VP3 - DPI1
567 assigned-clocks = <&k3_clks 152 1>,
571 assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */
618 #sound-dai-cells = <0>;
620 pinctrl-names = "default";
621 pinctrl-0 = <&mcasp10_pins_default>;
623 op-mode = <0>; /* MCASP_IIS_MODE */
624 tdm-slots = <2>;
625 auxclk-fs-ratio = <256>;
627 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
631 tx-num-evt = <0>;
632 rx-num-evt = <0>;
640 clock-frequency = <100000000>;
644 assigned-clocks = <&wiz0_pll1_refclk>;
645 assigned-clock-parents = <&cmn_refclk1>;
649 assigned-clocks = <&wiz0_refclk_dig>;
650 assigned-clock-parents = <&cmn_refclk1>;
654 assigned-clocks = <&wiz1_pll1_refclk>;
655 assigned-clock-parents = <&cmn_refclk1>;
659 assigned-clocks = <&wiz1_refclk_dig>;
660 assigned-clock-parents = <&cmn_refclk1>;
664 assigned-clocks = <&wiz2_pll1_refclk>;
665 assigned-clock-parents = <&cmn_refclk1>;
669 assigned-clocks = <&wiz2_refclk_dig>;
670 assigned-clock-parents = <&cmn_refclk1>;
674 assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
675 assigned-clock-parents = <&wiz0_pll1_refclk>;
679 cdns,num-lanes = <1>;
680 #phy-cells = <0>;
681 cdns,phy-type = <PHY_TYPE_PCIE>;
687 assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>;
688 assigned-clock-parents = <&wiz1_pll1_refclk>;
692 cdns,num-lanes = <2>;
693 #phy-cells = <0>;
694 cdns,phy-type = <PHY_TYPE_PCIE>;
700 assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>;
701 assigned-clock-parents = <&wiz2_pll1_refclk>;
705 cdns,num-lanes = <2>;
706 #phy-cells = <0>;
707 cdns,phy-type = <PHY_TYPE_PCIE>;
713 reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
715 phy-names = "pcie-phy";
716 num-lanes = <1>;
720 reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
722 phy-names = "pcie-phy";
723 num-lanes = <2>;
727 reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>;
729 phy-names = "pcie-phy";
730 num-lanes = <2>;
735 phy-names = "pcie-phy";
736 num-lanes = <1>;
742 phy-names = "pcie-phy";
743 num-lanes = <2>;
749 phy-names = "pcie-phy";
750 num-lanes = <2>;