Lines Matching +full:mbox +full:- +full:num +full:- +full:users
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
9 serdes_refclk: serdes-refclk {
10 #clock-cells = <0>;
11 compatible = "fixed-clock";
17 compatible = "mmio-sram";
19 #address-cells = <1>;
20 #size-cells = <1>;
23 atf-sram@0 {
28 scm_conf: scm-conf@100000 {
29 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
31 #address-cells = <1>;
32 #size-cells = <1>;
35 serdes_ln_ctrl: serdes-ln-ctrl@4080 {
36 compatible = "mmio-mux";
37 #mux-control-cells = <1>;
38 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
42 usb_serdes_mux: mux-controller@4000 {
43 compatible = "mmio-mux";
44 #mux-control-cells = <1>;
45 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
49 gic500: interrupt-controller@1800000 {
50 compatible = "arm,gic-v3";
51 #address-cells = <2>;
52 #size-cells = <2>;
54 #interrupt-cells = <3>;
55 interrupt-controller;
62 gic_its: msi-controller@1820000 {
63 compatible = "arm,gic-v3-its";
65 socionext,synquacer-pre-its = <0x1000000 0x400000>;
66 msi-controller;
67 #msi-cells = <1>;
71 main_gpio_intr: interrupt-controller@a00000 {
72 compatible = "ti,sci-intr";
74 ti,intr-trigger-type = <1>;
75 interrupt-controller;
76 interrupt-parent = <&gic500>;
77 #interrupt-cells = <1>;
79 ti,sci-dev-id = <131>;
80 ti,interrupt-ranges = <8 392 56>;
84 compatible = "simple-mfd";
85 #address-cells = <2>;
86 #size-cells = <2>;
88 ti,sci-dev-id = <199>;
89 dma-coherent;
90 dma-ranges;
92 main_navss_intr: interrupt-controller@310e0000 {
93 compatible = "ti,sci-intr";
95 ti,intr-trigger-type = <4>;
96 interrupt-controller;
97 interrupt-parent = <&gic500>;
98 #interrupt-cells = <1>;
100 ti,sci-dev-id = <213>;
101 ti,interrupt-ranges = <0 64 64>,
106 main_udmass_inta: msi-controller@33d00000 {
107 compatible = "ti,sci-inta";
109 interrupt-controller;
110 #interrupt-cells = <0>;
111 interrupt-parent = <&main_navss_intr>;
112 msi-controller;
114 ti,sci-dev-id = <209>;
115 ti,interrupt-ranges = <0 0 256>;
119 compatible = "ti,am654-secure-proxy";
120 #mbox-cells = <1>;
121 reg-names = "target_data", "rt", "scfg";
125 interrupt-names = "rx_011";
130 compatible = "ti,am654-hwspinlock";
132 #hwlock-cells = <1>;
136 compatible = "ti,am654-mailbox";
138 #mbox-cells = <1>;
139 ti,mbox-num-users = <4>;
140 ti,mbox-num-fifos = <16>;
141 interrupt-parent = <&main_navss_intr>;
145 compatible = "ti,am654-mailbox";
147 #mbox-cells = <1>;
148 ti,mbox-num-users = <4>;
149 ti,mbox-num-fifos = <16>;
150 interrupt-parent = <&main_navss_intr>;
154 compatible = "ti,am654-mailbox";
156 #mbox-cells = <1>;
157 ti,mbox-num-users = <4>;
158 ti,mbox-num-fifos = <16>;
159 interrupt-parent = <&main_navss_intr>;
163 compatible = "ti,am654-mailbox";
165 #mbox-cells = <1>;
166 ti,mbox-num-users = <4>;
167 ti,mbox-num-fifos = <16>;
168 interrupt-parent = <&main_navss_intr>;
172 compatible = "ti,am654-mailbox";
174 #mbox-cells = <1>;
175 ti,mbox-num-users = <4>;
176 ti,mbox-num-fifos = <16>;
177 interrupt-parent = <&main_navss_intr>;
181 compatible = "ti,am654-mailbox";
183 #mbox-cells = <1>;
184 ti,mbox-num-users = <4>;
185 ti,mbox-num-fifos = <16>;
186 interrupt-parent = <&main_navss_intr>;
190 compatible = "ti,am654-mailbox";
192 #mbox-cells = <1>;
193 ti,mbox-num-users = <4>;
194 ti,mbox-num-fifos = <16>;
195 interrupt-parent = <&main_navss_intr>;
199 compatible = "ti,am654-mailbox";
201 #mbox-cells = <1>;
202 ti,mbox-num-users = <4>;
203 ti,mbox-num-fifos = <16>;
204 interrupt-parent = <&main_navss_intr>;
208 compatible = "ti,am654-mailbox";
210 #mbox-cells = <1>;
211 ti,mbox-num-users = <4>;
212 ti,mbox-num-fifos = <16>;
213 interrupt-parent = <&main_navss_intr>;
217 compatible = "ti,am654-mailbox";
219 #mbox-cells = <1>;
220 ti,mbox-num-users = <4>;
221 ti,mbox-num-fifos = <16>;
222 interrupt-parent = <&main_navss_intr>;
226 compatible = "ti,am654-mailbox";
228 #mbox-cells = <1>;
229 ti,mbox-num-users = <4>;
230 ti,mbox-num-fifos = <16>;
231 interrupt-parent = <&main_navss_intr>;
235 compatible = "ti,am654-mailbox";
237 #mbox-cells = <1>;
238 ti,mbox-num-users = <4>;
239 ti,mbox-num-fifos = <16>;
240 interrupt-parent = <&main_navss_intr>;
244 compatible = "ti,am654-navss-ringacc";
249 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
250 ti,num-rings = <1024>;
251 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
253 ti,sci-dev-id = <211>;
254 msi-parent = <&main_udmass_inta>;
257 main_udmap: dma-controller@31150000 {
258 compatible = "ti,j721e-navss-main-udmap";
262 reg-names = "gcfg", "rchanrt", "tchanrt";
263 msi-parent = <&main_udmass_inta>;
264 #dma-cells = <1>;
267 ti,sci-dev-id = <212>;
270 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
273 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
276 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
280 compatible = "ti,j721e-cpts";
282 reg-names = "cpts";
284 clock-names = "cpts";
285 interrupts-extended = <&main_navss_intr 391>;
286 interrupt-names = "cpts";
287 ti,cpts-periodic-outputs = <6>;
288 ti,cpts-ext-ts-inputs = <8>;
293 compatible = "pinctrl-single";
296 #pinctrl-cells = <1>;
297 pinctrl-single,register-width = <32>;
298 pinctrl-single,function-mask = <0xffffffff>;
302 compatible = "ti,j721e-uart", "ti,am654-uart";
305 clock-frequency = <48000000>;
306 current-speed = <115200>;
307 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
309 clock-names = "fclk";
313 compatible = "ti,j721e-uart", "ti,am654-uart";
316 clock-frequency = <48000000>;
317 current-speed = <115200>;
318 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
320 clock-names = "fclk";
324 compatible = "ti,j721e-uart", "ti,am654-uart";
327 clock-frequency = <48000000>;
328 current-speed = <115200>;
329 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
331 clock-names = "fclk";
335 compatible = "ti,j721e-uart", "ti,am654-uart";
338 clock-frequency = <48000000>;
339 current-speed = <115200>;
340 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
342 clock-names = "fclk";
346 compatible = "ti,j721e-uart", "ti,am654-uart";
349 clock-frequency = <48000000>;
350 current-speed = <115200>;
351 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
353 clock-names = "fclk";
357 compatible = "ti,j721e-uart", "ti,am654-uart";
360 clock-frequency = <48000000>;
361 current-speed = <115200>;
362 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
364 clock-names = "fclk";
368 compatible = "ti,j721e-uart", "ti,am654-uart";
371 clock-frequency = <48000000>;
372 current-speed = <115200>;
373 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
375 clock-names = "fclk";
379 compatible = "ti,j721e-uart", "ti,am654-uart";
382 clock-frequency = <48000000>;
383 current-speed = <115200>;
384 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
386 clock-names = "fclk";
390 compatible = "ti,j721e-uart", "ti,am654-uart";
393 clock-frequency = <48000000>;
394 current-speed = <115200>;
395 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
397 clock-names = "fclk";
401 compatible = "ti,j721e-uart", "ti,am654-uart";
404 clock-frequency = <48000000>;
405 current-speed = <115200>;
406 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
408 clock-names = "fclk";
412 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
415 #address-cells = <1>;
416 #size-cells = <0>;
417 clock-names = "fck";
419 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
423 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
426 #address-cells = <1>;
427 #size-cells = <0>;
428 clock-names = "fck";
430 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
434 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
437 #address-cells = <1>;
438 #size-cells = <0>;
439 clock-names = "fck";
441 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
445 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
448 #address-cells = <1>;
449 #size-cells = <0>;
450 clock-names = "fck";
452 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
456 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
459 #address-cells = <1>;
460 #size-cells = <0>;
461 clock-names = "fck";
463 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
467 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
470 #address-cells = <1>;
471 #size-cells = <0>;
472 clock-names = "fck";
474 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
478 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
481 #address-cells = <1>;
482 #size-cells = <0>;
483 clock-names = "fck";
485 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
489 compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit";
492 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
493 clock-names = "clk_ahb", "clk_xin";
495 ti,otap-del-sel-legacy = <0x0>;
496 ti,otap-del-sel-mmc-hs = <0x0>;
497 ti,otap-del-sel-ddr52 = <0x6>;
498 ti,otap-del-sel-hs200 = <0x8>;
499 ti,otap-del-sel-hs400 = <0x5>;
500 ti,itap-del-sel-legacy = <0x10>;
501 ti,itap-del-sel-mmc-hs = <0xa>;
502 ti,strobe-sel = <0x77>;
503 ti,clkbuf-sel = <0x7>;
504 ti,trm-icp = <0x8>;
505 bus-width = <8>;
506 mmc-ddr-1_8v;
507 mmc-hs200-1_8v;
508 mmc-hs400-1_8v;
509 dma-coherent;
513 compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit";
516 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
517 clock-names = "clk_ahb", "clk_xin";
519 ti,otap-del-sel-legacy = <0x0>;
520 ti,otap-del-sel-sd-hs = <0x0>;
521 ti,otap-del-sel-sdr12 = <0xf>;
522 ti,otap-del-sel-sdr25 = <0xf>;
523 ti,otap-del-sel-sdr50 = <0xc>;
524 ti,otap-del-sel-sdr104 = <0x5>;
525 ti,otap-del-sel-ddr50 = <0xc>;
526 ti,itap-del-sel-legacy = <0x0>;
527 ti,itap-del-sel-sd-hs = <0x0>;
528 ti,itap-del-sel-sdr12 = <0x0>;
529 ti,itap-del-sel-sdr25 = <0x0>;
530 ti,clkbuf-sel = <0x7>;
531 ti,trm-icp = <0x8>;
532 dma-coherent;
536 compatible = "ti,j721e-wiz-10g";
537 #address-cells = <1>;
538 #size-cells = <1>;
539 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
541 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
542 num-lanes = <4>;
543 #reset-cells = <1>;
546 assigned-clocks = <&k3_clks 292 85>;
547 assigned-clock-parents = <&k3_clks 292 89>;
549 wiz0_pll0_refclk: pll0-refclk {
551 clock-output-names = "wiz0_pll0_refclk";
552 #clock-cells = <0>;
553 assigned-clocks = <&wiz0_pll0_refclk>;
554 assigned-clock-parents = <&k3_clks 292 85>;
557 wiz0_pll1_refclk: pll1-refclk {
559 clock-output-names = "wiz0_pll1_refclk";
560 #clock-cells = <0>;
561 assigned-clocks = <&wiz0_pll1_refclk>;
562 assigned-clock-parents = <&k3_clks 292 85>;
565 wiz0_refclk_dig: refclk-dig {
567 clock-output-names = "wiz0_refclk_dig";
568 #clock-cells = <0>;
569 assigned-clocks = <&wiz0_refclk_dig>;
570 assigned-clock-parents = <&k3_clks 292 85>;
573 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
575 #clock-cells = <0>;
579 compatible = "ti,j721e-serdes-10g";
581 reg-names = "torrent_phy";
583 reset-names = "torrent_reset";
585 clock-names = "refclk";
586 #address-cells = <1>;
587 #size-cells = <0>;
592 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
597 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
598 interrupt-names = "link_state";
601 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
602 max-link-speed = <3>;
603 num-lanes = <4>;
604 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
606 clock-names = "fck";
607 #address-cells = <3>;
608 #size-cells = <2>;
609 bus-range = <0x0 0xf>;
610 cdns,no-bar-match-nbits = <64>;
611 vendor-id = /bits/ 16 <0x104c>;
612 device-id = /bits/ 16 <0xb00f>;
613 msi-map = <0x0 &gic_its 0x0 0x10000>;
614 dma-coherent;
617 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
620 pcie1_ep: pcie-ep@2910000 {
621 compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep";
626 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
627 interrupt-names = "link_state";
629 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
630 max-link-speed = <3>;
631 num-lanes = <4>;
632 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
634 clock-names = "fck";
635 max-functions = /bits/ 8 <6>;
636 dma-coherent;
639 usbss0: cdns-usb@4104000 {
640 compatible = "ti,j721e-usb";
642 dma-coherent;
643 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
645 clock-names = "ref", "lpm";
646 assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */
647 assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */
648 #address-cells = <2>;
649 #size-cells = <2>;
657 reg-names = "otg", "xhci", "dev";
661 interrupt-names = "host",
664 maximum-speed = "super-speed";
666 cdns,phyrst-a-enable;
671 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
673 gpio-controller;
674 #gpio-cells = <2>;
675 interrupt-parent = <&main_gpio_intr>;
678 interrupt-controller;
679 #interrupt-cells = <2>;
681 ti,davinci-gpio-unbanked = <0>;
682 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
684 clock-names = "gpio";
688 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
690 gpio-controller;
691 #gpio-cells = <2>;
692 interrupt-parent = <&main_gpio_intr>;
695 interrupt-controller;
696 #interrupt-cells = <2>;
698 ti,davinci-gpio-unbanked = <0>;
699 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
701 clock-names = "gpio";
705 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
707 gpio-controller;
708 #gpio-cells = <2>;
709 interrupt-parent = <&main_gpio_intr>;
712 interrupt-controller;
713 #interrupt-cells = <2>;
715 ti,davinci-gpio-unbanked = <0>;
716 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
718 clock-names = "gpio";
722 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
724 gpio-controller;
725 #gpio-cells = <2>;
726 interrupt-parent = <&main_gpio_intr>;
729 interrupt-controller;
730 #interrupt-cells = <2>;
732 ti,davinci-gpio-unbanked = <0>;
733 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
735 clock-names = "gpio";
739 compatible = "ti,j7200-r5fss";
740 ti,cluster-mode = <1>;
741 #address-cells = <1>;
742 #size-cells = <1>;
745 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
748 compatible = "ti,j7200-r5f";
751 reg-names = "atcm", "btcm";
753 ti,sci-dev-id = <245>;
754 ti,sci-proc-ids = <0x06 0xff>;
756 firmware-name = "j7200-main-r5f0_0-fw";
757 ti,atcm-enable = <1>;
758 ti,btcm-enable = <1>;
763 compatible = "ti,j7200-r5f";
766 reg-names = "atcm", "btcm";
768 ti,sci-dev-id = <246>;
769 ti,sci-proc-ids = <0x07 0xff>;
771 firmware-name = "j7200-main-r5f0_1-fw";
772 ti,atcm-enable = <1>;
773 ti,btcm-enable = <1>;